Lines Matching refs:rate
51 struct rockchip_clk_pll *pll, unsigned long rate)
57 if (rate == rate_table[i].rate)
73 if (drate >= rate_table[i].rate)
74 return rate_table[i].rate;
78 return rate_table[i - 1].rate;
140 struct rockchip_pll_rate_table *rate)
145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
155 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
190 const struct rockchip_pll_rate_table *rate)
200 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
202 rate->postdiv2, rate->dsmpd, rate->frac);
205 cur.rate = 0;
214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
231 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
252 const struct rockchip_pll_rate_table *rate;
254 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
257 /* Get required rate settings from table */
258 rate = rockchip_get_pll_settings(pll, drate);
259 if (!rate) {
260 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
265 return rockchip_rk3036_pll_set_params(pll, rate);
299 const struct rockchip_pll_rate_table *rate;
307 rate = rockchip_get_pll_settings(pll, drate);
309 /* when no rate setting for the current rate, rely on clk_set_rate */
310 if (!rate)
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
322 rate->dsmpd, rate->frac);
324 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
325 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
326 rate->dsmpd != cur.dsmpd ||
327 (!cur.dsmpd && (rate->frac != cur.frac))) {
336 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
338 rockchip_rk3036_pll_set_params(pll, rate);
381 struct rockchip_pll_rate_table *rate)
386 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
388 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
392 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
396 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
425 const struct rockchip_pll_rate_table *rate)
434 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
435 __func__, rate->rate, rate->nr, rate->no, rate->nf);
438 cur.rate = 0;
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
453 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
457 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
460 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
467 udelay(RK3066_PLL_RESET_DELAY(rate->nr));
487 const struct rockchip_pll_rate_table *rate;
489 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
492 /* Get required rate settings from table */
493 rate = rockchip_get_pll_settings(pll, drate);
494 if (!rate) {
495 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
500 return rockchip_rk3066_pll_set_params(pll, rate);
534 const struct rockchip_pll_rate_table *rate;
542 rate = rockchip_get_pll_settings(pll, drate);
544 /* when no rate setting for the current rate, rely on clk_set_rate */
545 if (!rate)
551 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
552 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
553 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
554 || rate->nb != cur.nb) {
555 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
557 rockchip_rk3066_pll_set_params(pll, rate);
620 struct rockchip_pll_rate_table *rate)
625 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
629 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
631 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
633 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
637 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
641 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
672 const struct rockchip_pll_rate_table *rate)
682 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
683 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
684 rate->postdiv2, rate->dsmpd, rate->frac);
687 cur.rate = 0;
696 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
700 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
702 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
704 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
711 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
714 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
736 const struct rockchip_pll_rate_table *rate;
738 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
741 /* Get required rate settings from table */
742 rate = rockchip_get_pll_settings(pll, drate);
743 if (!rate) {
744 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
749 return rockchip_rk3399_pll_set_params(pll, rate);
783 const struct rockchip_pll_rate_table *rate;
791 rate = rockchip_get_pll_settings(pll, drate);
793 /* when no rate setting for the current rate, rely on clk_set_rate */
794 if (!rate)
805 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
806 rate->dsmpd, rate->frac);
808 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
809 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
810 rate->dsmpd != cur.dsmpd ||
811 (!cur.dsmpd && (rate->frac != cur.frac))) {
820 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
822 rockchip_rk3399_pll_set_params(pll, rate);
927 for (len = 0; rate_table[len].rate != 0; )
936 "%s: could not allocate rate table for %s\n",