Lines Matching refs:pll
51 struct rockchip_clk_pll *pll, unsigned long rate)
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
56 for (i = 0; i < pll->rate_count; i++) {
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
72 for (i = 0; i < pll->rate_count; i++) {
82 * Wait for the pll to reach the locked state.
86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
88 struct regmap *grf = pll->ctx->grf;
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
93 val & BIT(pll->lock_shift), 0, 1000);
95 pr_err("%s: timeout waiting for pll to lock\n", __func__);
120 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
134 pr_err("%s: timeout waiting for pll to lock\n", __func__);
139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
166 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
170 rockchip_rk3036_pll_get_params(pll, &cur);
189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
192 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
193 struct clk_mux *pll_mux = &pll->pll_mux;
204 rockchip_rk3036_pll_get_params(pll, &cur);
213 /* update pll values */
218 pll->reg_base + RK3036_PLLCON(0));
226 pll->reg_base + RK3036_PLLCON(1));
229 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
232 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
234 /* wait for the pll to lock */
235 ret = rockchip_rk3036_pll_wait_lock(pll);
237 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
239 rockchip_rk3036_pll_set_params(pll, &cur);
251 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
258 rate = rockchip_get_pll_settings(pll, drate);
260 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
265 return rockchip_rk3036_pll_set_params(pll, rate);
270 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
273 pll->reg_base + RK3036_PLLCON(1));
274 rockchip_rk3036_pll_wait_lock(pll);
281 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
285 pll->reg_base + RK3036_PLLCON(1));
290 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
291 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
298 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
303 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
307 rate = rockchip_get_pll_settings(pll, drate);
313 rockchip_rk3036_pll_get_params(pll, &cur);
315 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
336 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
338 rockchip_rk3036_pll_set_params(pll, rate);
380 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
385 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
391 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
395 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
403 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
408 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
410 pr_debug("%s: pll %s is bypassed\n", __func__,
415 rockchip_rk3066_pll_get_params(pll, &cur);
424 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
427 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
428 struct clk_mux *pll_mux = &pll->pll_mux;
437 rockchip_rk3066_pll_get_params(pll, &cur);
448 pll->reg_base + RK3066_PLLCON(3));
450 /* update pll values */
455 pll->reg_base + RK3066_PLLCON(0));
459 pll->reg_base + RK3066_PLLCON(1));
462 pll->reg_base + RK3066_PLLCON(2));
466 pll->reg_base + RK3066_PLLCON(3));
469 /* wait for the pll to lock */
470 ret = rockchip_pll_wait_lock(pll);
472 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
474 rockchip_rk3066_pll_set_params(pll, &cur);
486 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
493 rate = rockchip_get_pll_settings(pll, drate);
495 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
500 return rockchip_rk3066_pll_set_params(pll, rate);
505 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
508 pll->reg_base + RK3066_PLLCON(3));
509 rockchip_pll_wait_lock(pll);
516 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
520 pll->reg_base + RK3066_PLLCON(3));
525 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
526 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
533 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
538 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
542 rate = rockchip_get_pll_settings(pll, drate);
548 rockchip_rk3066_pll_get_params(pll, &cur);
550 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
555 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
557 rockchip_rk3066_pll_set_params(pll, rate);
600 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
609 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
614 pr_err("%s: timeout waiting for pll to lock\n", __func__);
619 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
624 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
628 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
636 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
640 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
648 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
652 rockchip_rk3399_pll_get_params(pll, &cur);
671 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
674 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
675 struct clk_mux *pll_mux = &pll->pll_mux;
686 rockchip_rk3399_pll_get_params(pll, &cur);
695 /* update pll values */
698 pll->reg_base + RK3399_PLLCON(0));
706 pll->reg_base + RK3399_PLLCON(1));
709 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
712 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
716 pll->reg_base + RK3399_PLLCON(3));
718 /* wait for the pll to lock */
719 ret = rockchip_rk3399_pll_wait_lock(pll);
721 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
723 rockchip_rk3399_pll_set_params(pll, &cur);
735 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
742 rate = rockchip_get_pll_settings(pll, drate);
744 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
749 return rockchip_rk3399_pll_set_params(pll, rate);
754 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
757 pll->reg_base + RK3399_PLLCON(3));
758 rockchip_rk3399_pll_wait_lock(pll);
765 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
769 pll->reg_base + RK3399_PLLCON(3));
774 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
775 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
782 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
787 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
791 rate = rockchip_get_pll_settings(pll, drate);
797 rockchip_rk3399_pll_get_params(pll, &cur);
799 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
820 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
822 rockchip_rk3399_pll_set_params(pll, rate);
846 * Common registering of pll clocks
859 struct rockchip_clk_pll *pll;
870 /* name the actual pll */
873 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
874 if (!pll)
877 /* create the mux on top of the real pll */
878 pll->pll_mux_ops = &clk_mux_ops;
879 pll_mux = &pll->pll_mux;
896 /* the actual muxing is xin24m, pll-output, xin32k */
903 init.ops = pll->pll_mux_ops;
914 /* now create the actual pll */
930 pll->rate_count = len;
931 pll->rate_table = kmemdup(rate_table,
932 pll->rate_count *
935 WARN(!pll->rate_table,
943 if (!pll->rate_table)
949 if (!pll->rate_table || IS_ERR(ctx->grf))
955 if (!pll->rate_table)
961 pr_warn("%s: Unknown pll type for pll clk %s\n",
965 pll->hw.init = &init;
966 pll->type = pll_type;
967 pll->reg_base = ctx->reg_base + con_offset;
968 pll->lock_offset = grf_lock_offset;
969 pll->lock_shift = lock_shift;
970 pll->flags = clk_pll_flags;
971 pll->lock = &ctx->lock;
972 pll->ctx = ctx;
974 pll_clk = clk_register(NULL, &pll->hw);
976 pr_err("%s: failed to register pll clock %s : %ld\n",
984 kfree(pll->rate_table);
988 kfree(pll);