Lines Matching refs:init
358 .init = rockchip_rk3036_pll_init,
577 .init = rockchip_rk3066_pll_init,
842 .init = rockchip_rk3399_pll_init,
858 struct clk_init_data init;
888 pll_mux->hw.init = &init;
901 init.name = name;
902 init.flags = CLK_SET_RATE_PARENT;
903 init.ops = pll->pll_mux_ops;
904 init.parent_names = pll_parents;
906 init.num_parents = 2;
908 init.num_parents = ARRAY_SIZE(pll_parents);
915 init.name = pll_name;
918 init.flags = flags | CLK_IGNORE_UNUSED;
920 init.parent_names = &parent_names[0];
921 init.num_parents = 1;
944 init.ops = &rockchip_rk3036_pll_clk_norate_ops;
946 init.ops = &rockchip_rk3036_pll_clk_ops;
950 init.ops = &rockchip_rk3066_pll_clk_norate_ops;
952 init.ops = &rockchip_rk3066_pll_clk_ops;
956 init.ops = &rockchip_rk3399_pll_clk_norate_ops;
958 init.ops = &rockchip_rk3399_pll_clk_ops;
965 pll->hw.init = &init;