clk-pll.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/rockchip/clk-pll.c

Lines Matching defs:reg_base
34 	void __iomem		*reg_base;
129 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
144 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
150 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
158 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
218 		       pll->reg_base + RK3036_PLLCON(0));
226 		       pll->reg_base + RK3036_PLLCON(1));
229 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
232 	writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
273 	       pll->reg_base + RK3036_PLLCON(1));
285 	       pll->reg_base + RK3036_PLLCON(1));
291 	u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
385 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
391 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
395 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
408 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
448 	       pll->reg_base + RK3066_PLLCON(3));
455 	       pll->reg_base + RK3066_PLLCON(0));
459 		       pll->reg_base + RK3066_PLLCON(1));
462 		       pll->reg_base + RK3066_PLLCON(2));
466 	       pll->reg_base + RK3066_PLLCON(3));
508 	       pll->reg_base + RK3066_PLLCON(3));
520 	       pll->reg_base + RK3066_PLLCON(3));
526 	u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
609 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
624 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
628 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
636 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
640 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
698 		       pll->reg_base + RK3399_PLLCON(0));
706 		       pll->reg_base + RK3399_PLLCON(1));
709 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
712 	writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
716 		       pll->reg_base + RK3399_PLLCON(3));
757 	       pll->reg_base + RK3399_PLLCON(3));
769 	       pll->reg_base + RK3399_PLLCON(3));
775 	u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
880 	pll_mux->reg = ctx->reg_base + mode_offset;
967 	pll->reg_base = ctx->reg_base + con_offset;