clk-cpu.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/rockchip/clk-cpu.c

Lines Matching refs:cpuclk
72 			    struct rockchip_cpuclk *cpuclk, unsigned long rate)
75 							cpuclk->rate_table;
78 	for (i = 0; i < cpuclk->rate_count; i++) {
89 	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
90 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
91 	u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
102 static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
116 		writel(clksel->val, cpuclk->reg_base + clksel->reg);
120 static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
123 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
129 	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
131 		pr_err("%s: Invalid rate : %lu for cpuclk\n",
136 	alt_prate = clk_get_rate(cpuclk->alt_parent);
138 	spin_lock_irqsave(cpuclk->lock, flags);
170 		       cpuclk->reg_base + reg_data->core_reg);
176 		       cpuclk->reg_base + reg_data->core_reg);
179 	spin_unlock_irqrestore(cpuclk->lock, flags);
183 static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
186 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
190 	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
192 		pr_err("%s: Invalid rate : %lu for cpuclk\n",
197 	spin_lock_irqsave(cpuclk->lock, flags);
200 		rockchip_cpuclk_set_dividers(cpuclk, rate);
214 	       cpuclk->reg_base + reg_data->core_reg);
217 		rockchip_cpuclk_set_dividers(cpuclk, rate);
219 	spin_unlock_irqrestore(cpuclk->lock, flags);
225  * of cpuclk is to be changed. This notifier handles the setting up all
233 	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
239 		ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
241 		ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
252 	struct rockchip_cpuclk *cpuclk;
262 	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
263 	if (!cpuclk)
279 	cpuclk->reg_base = reg_base;
280 	cpuclk->lock = lock;
281 	cpuclk->reg_data = reg_data;
282 	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
283 	cpuclk->hw.init = &init;
285 	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
286 	if (!cpuclk->alt_parent) {
293 	ret = clk_prepare_enable(cpuclk->alt_parent);
309 	ret = clk_notifier_register(clk, &cpuclk->clk_nb);
317 		cpuclk->rate_count = nrates;
318 		cpuclk->rate_table = kmemdup(rates,
321 		if (!cpuclk->rate_table) {
327 	cclk = clk_register(NULL, &cpuclk->hw);
329 		pr_err("%s: could not register cpuclk %s\n", __func__,	name);
337 	kfree(cpuclk->rate_table);
339 	clk_notifier_unregister(clk, &cpuclk->clk_nb);
341 	clk_disable_unprepare(cpuclk->alt_parent);
343 	kfree(cpuclk);