Lines Matching defs:clock
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
133 * @notifiers: Notifier chain to save/restore clock state for system resume
172 * struct mstp_clock - MSTP gating clock
174 * @index: MSTP clock number
187 struct mstp_clock *clock = to_mstp_clock(hw);
188 struct cpg_mssr_priv *priv = clock->priv;
189 unsigned int reg = clock->index / 32;
190 unsigned int bit = clock->index % 32;
253 struct mstp_clock *clock = to_mstp_clock(hw);
254 struct cpg_mssr_priv *priv = clock->priv;
258 value = readb(priv->base + priv->control_regs[clock->index / 32]);
260 value = readl(priv->base + priv->status_regs[clock->index / 32]);
262 return !(value & BIT(clock->index % 32));
287 dev_err(dev, "Invalid %s clock index %u\n", type,
304 dev_err(dev, "Invalid %s clock index %u\n", type,
312 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
317 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
320 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
339 /* Skip NULLified clock */
386 dev_err(dev, "%s has unsupported core clock type %u\n",
394 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
399 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
407 struct mstp_clock *clock = NULL;
421 /* Skip NULLified clock */
431 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
432 if (!clock) {
444 clock->index = id - priv->num_core_clks;
445 clock->priv = priv;
446 clock->hw.init = &init;
450 cpg_mstp_clock_is_enabled(&clock->hw)) {
457 clk = clk_register(NULL, &clock->hw);
461 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
463 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
467 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
469 kfree(clock);
513 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
517 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
604 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */