Lines Matching refs:core
548 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
557 parent = clks[core->parent & 0xffff]; /* some types use high bits */
561 switch (core->type) {
616 return cpg_sd_clk_register(core->name, base, core->offset,
655 if (cpg_mode & BIT(core->offset)) {
656 div = core->div & 0xffff;
658 parent = clks[core->parent >> 16];
661 div = core->div >> 16;
667 return cpg_z_clk_register(core->name, __clk_get_name(parent),
668 base, core->div, core->offset);
674 div = cpg_pll_config->osc_prediv * core->div;
683 div = core->div & 0xffff;
685 parent = clks[core->parent >> 16];
688 div = core->div >> 16;
693 return clk_register_divider_table(NULL, core->name,
700 return cpg_rpc_clk_register(core->name, base,
704 return cpg_rpcd2_clk_register(core->name, base,
711 return clk_register_fixed_factor(NULL, core->name,