Lines Matching defs:clock
83 * Traits of this clock:
156 * clock change completion.
286 struct sd_clock *clock = to_sd_clock(hw);
288 cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
289 clock->div_table[clock->cur_div_idx].val &
297 struct sd_clock *clock = to_sd_clock(hw);
299 cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
304 struct sd_clock *clock = to_sd_clock(hw);
306 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
312 struct sd_clock *clock = to_sd_clock(hw);
315 clock->div_table[clock->cur_div_idx].div);
322 struct sd_clock *clock = to_sd_clock(hw);
326 for (i = 0; i < clock->div_num; i++) {
328 clock->div_table[i].div);
350 struct sd_clock *clock = to_sd_clock(hw);
353 for (i = 0; i < clock->div_num; i++)
355 clock->div_table[i].div))
358 if (i >= clock->div_num)
361 clock->cur_div_idx = i;
363 cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
364 clock->div_table[i].val &
383 #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
390 struct sd_clock *clock;
394 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
395 if (!clock)
404 clock->csn.reg = base + offset;
405 clock->hw.init = &init;
406 clock->div_table = cpg_sd_div_table;
407 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
410 clock->div_table++;
411 clock->div_num--;
414 val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
415 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
416 writel(val, clock->csn.reg);
418 clk = clk_register(NULL, &clock->hw);
422 cpg_simple_notifier_register(notifiers, &clock->csn);
426 kfree(clock);
568 * PLL0 is a configurable multiplier clock. Register it as a
569 * fixed factor clock for now as there's no generic multiplier
570 * clock implementation and we currently have no need to change
586 * PLL2 is a configurable multiplier clock. Register it as a
587 * fixed factor clock for now as there's no generic multiplier
588 * clock implementation and we currently have no need to change
604 * PLL4 is a configurable multiplier clock. Register it as a
605 * fixed factor clock for now as there's no generic multiplier
606 * clock implementation and we currently have no need to change
645 /* Select parent clock of RCLK by MD28 */