Lines Matching defs:mult
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
57 unsigned int mult;
61 mult = 32 - val;
63 return div_u64((u64)parent_rate * mult, 32);
70 unsigned int min_mult, max_mult, mult;
77 mult = div64_ul(req->rate * 32ULL, prate);
78 mult = clamp(mult, min_mult, max_mult);
80 req->rate = div_u64((u64)prate * mult, 32);
88 unsigned int mult;
92 mult = div64_ul(rate * 32ULL, parent_rate);
93 mult = clamp(mult, 1U, 32U);
100 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
177 fixed->mult = 1;
284 unsigned int mult = 1;
307 mult = cpg_pll_config->pll0_mult;
309 if (!mult) {
312 mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >>
318 mult = cpg_pll_config->pll1_mult / 2;
322 mult = cpg_pll_config->pll3_mult;
370 0, mult, div);