Lines Matching refs:core
163 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
172 parent = clks[core->parent & 0xffff]; /* some types use high bits */
176 switch (core->type) {
187 value = readl(base + core->offset);
201 if (cpg_mode & BIT(core->offset)) {
202 div = core->div & 0xffff;
204 parent = clks[core->parent >> 16];
207 div = core->div >> 16;
216 div = cpg_pll_config->osc_prediv * core->div;
223 return clk_register_fixed_factor(NULL, core->name,