Lines Matching defs:clock
27 * struct div6_clock - CPG 6 bit divider clock
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
33 * @nb: Notifier block to save/restore clock state for system resume
50 struct div6_clock *clock = to_div6_clock(hw);
53 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
54 | CPG_DIV6_DIV(clock->div - 1);
55 writel(val, clock->reg);
62 struct div6_clock *clock = to_div6_clock(hw);
65 val = readl(clock->reg);
69 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
71 * clock
75 writel(val, clock->reg);
80 struct div6_clock *clock = to_div6_clock(hw);
82 return !(readl(clock->reg) & CPG_DIV6_CKSTP);
88 struct div6_clock *clock = to_div6_clock(hw);
90 return parent_rate / clock->div;
116 struct div6_clock *clock = to_div6_clock(hw);
120 clock->div = div;
122 val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
123 /* Only program the new divisor if the clock isn't stopped. */
125 writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
132 struct div6_clock *clock = to_div6_clock(hw);
136 if (clock->src_width == 0)
139 hw_index = (readl(clock->reg) >> clock->src_shift) &
140 (BIT(clock->src_width) - 1);
142 if (clock->parents[i] == hw_index)
146 pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
153 struct div6_clock *clock = to_div6_clock(hw);
160 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
161 hw_index = clock->parents[index];
163 writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
164 clock->reg);
183 struct div6_clock *clock = container_of(nb, struct div6_clock, nb);
194 if (__clk_get_enable_count(clock->hw.clk))
195 cpg_div6_clock_enable(&clock->hw);
197 cpg_div6_clock_disable(&clock->hw);
205 * cpg_div6_register - Register a DIV6 clock
206 * @name: Name of the DIV6 clock
207 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
209 * @reg: Mapped register used to control the DIV6 clock
220 struct div6_clock *clock;
224 clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);
225 if (!clock)
228 clock->reg = reg;
231 * Read the divisor. Disabling the clock overwrites the divisor, so we
234 clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
238 /* fixed parent clock */
239 clock->src_shift = clock->src_width = 0;
242 /* clock with EXSRC bits 6-7 */
243 clock->src_shift = 6;
244 clock->src_width = 2;
248 clock->src_shift = 12;
249 clock->src_width = 3;
252 pr_err("%s: invalid number of parents for DIV6 clock %s\n",
262 clock->parents[valid_parents] = i;
267 /* Register the clock. */
274 clock->hw.init = &init;
276 clk = clk_register(NULL, &clock->hw);
281 clock->nb.notifier_call = cpg_div6_clock_notifier_call;
282 raw_notifier_chain_register(notifiers, &clock->nb);
288 kfree(clock);
303 pr_err("%s: no parent found for %pOFn DIV6 clock\n",
315 pr_err("%s: failed to map %pOFn DIV6 clock register\n",
321 of_property_read_string(np, "clock-output-names", &clk_name);
328 pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
343 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);