Lines Matching defs:rcg
20 #include "clk-rcg.h"
45 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
46 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
47 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
69 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
78 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
83 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
91 if (cfg == rcg->parent_map[i].cfg)
100 static int update_config(struct clk_rcg2 *rcg)
104 struct clk_hw *hw = &rcg->clkr.hw;
107 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
114 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
122 WARN(1, "%s: rcg didn't update its configuration.", name);
128 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
130 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
132 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
137 return update_config(rcg);
162 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
165 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
167 if (rcg->mnd_width) {
168 mask = BIT(rcg->mnd_width) - 1;
169 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
171 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
179 mask = BIT(rcg->hid_width) - 1;
192 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
209 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
246 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
248 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
254 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
256 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
259 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
262 struct clk_hw *hw = &rcg->clkr.hw;
263 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
268 if (rcg->mnd_width && f->n) {
269 mask = BIT(rcg->mnd_width) - 1;
270 ret = regmap_update_bits(rcg->clkr.regmap,
271 RCG_M_OFFSET(rcg), mask, f->m);
275 ret = regmap_update_bits(rcg->clkr.regmap,
276 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
289 ret = regmap_update_bits(rcg->clkr.regmap,
290 RCG_D_OFFSET(rcg), mask, not2d_val);
295 mask = BIT(rcg->hid_width) - 1;
298 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
299 if (rcg->mnd_width && f->n && (f->m != f->n))
301 return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
305 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
309 ret = __clk_rcg2_configure(rcg, f);
313 return update_config(rcg);
319 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
324 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
327 f = qcom_find_freq(rcg->freq_tbl, rate);
336 return clk_rcg2_configure(rcg, f);
415 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
416 struct freq_tbl f = *rcg->freq_tbl;
421 u32 mask = BIT(rcg->hid_width) - 1;
437 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
445 return clk_rcg2_configure(rcg, &f);
461 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
462 const struct freq_tbl *f = rcg->freq_tbl;
466 u32 mask = BIT(rcg->hid_width) - 1;
468 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
487 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
515 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
516 const struct freq_tbl *f = rcg->freq_tbl;
517 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
519 u32 mask = BIT(rcg->hid_width) - 1;
539 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
540 struct freq_tbl f = *rcg->freq_tbl;
542 u32 mask = BIT(rcg->hid_width) - 1;
549 return clk_rcg2_configure(rcg, &f);
573 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
575 u32 mask = BIT(rcg->hid_width) - 1;
596 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
600 u32 mask = BIT(rcg->hid_width) - 1;
608 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
613 if (cfg == rcg->parent_map[i].cfg) {
614 f.src = rcg->parent_map[i].src;
615 return clk_rcg2_configure(rcg, &f);
675 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
680 u32 mask = BIT(rcg->hid_width) - 1;
684 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
689 if (cfg == rcg->parent_map[i].cfg) {
690 f.src = rcg->parent_map[i].src;
701 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
709 return clk_rcg2_configure(rcg, &f);
783 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
788 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
789 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
793 return update_config(rcg);
820 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
824 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
843 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
845 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
852 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
859 ret = clk_rcg2_configure(rcg, f);
869 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
872 f = qcom_find_freq(rcg->freq_tbl, rate);
881 return __clk_rcg2_configure(rcg, f);
894 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
905 ret = update_config(rcg);
914 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
921 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
933 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
934 rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
936 update_config(rcg);
941 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
960 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
966 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
968 mask = BIT(rcg->hid_width) - 1;
978 if (src == rcg->parent_map[i].cfg) {
979 f->src = rcg->parent_map[i].src;
980 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
988 mask = BIT(rcg->mnd_width) - 1;
989 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
994 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
1005 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
1014 rcg->freq_tbl = freq_tbl;
1017 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
1025 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1028 if (!rcg->freq_tbl) {
1029 ret = clk_rcg2_dfs_populate_freq_table(rcg);
1043 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1046 regmap_read(rcg->clkr.regmap,
1047 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
1051 if (rcg->freq_tbl)
1052 return rcg->freq_tbl[level].freq;
1061 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
1064 mask = BIT(rcg->hid_width) - 1;
1072 mask = BIT(rcg->mnd_width) - 1;
1073 regmap_read(rcg->clkr.regmap,
1074 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
1077 regmap_read(rcg->clkr.regmap,
1078 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
1097 struct clk_rcg2 *rcg = data->rcg;
1102 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
1116 rcg->freq_tbl = NULL;
1139 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1141 u32 mask = BIT(rcg->hid_width) - 1;
1147 GENMASK(rcg->mnd_width - 1, 0),
1148 GENMASK(rcg->mnd_width - 1, 0), &den, &num);
1153 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
1159 if (cfg == rcg->parent_map[i].cfg) {
1160 f.src = rcg->parent_map[i].src;
1177 return clk_rcg2_configure(rcg, &f);
1189 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1195 GENMASK(rcg->mnd_width - 1, 0),
1196 GENMASK(rcg->mnd_width - 1, 0), &den, &num);