clk-pll.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/qcom/clk-pll.c

Lines Matching refs:pll
17 #include "clk-pll.h"
26 	struct clk_pll *pll = to_clk_pll(hw);
31 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
40 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
52 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
61 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
67 	struct clk_pll *pll = to_clk_pll(hw);
71 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
76 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
82 	struct clk_pll *pll = to_clk_pll(hw);
87 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);
88 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);
89 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);
102 	if (pll->post_div_width) {
103 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);
104 		config >>= pll->post_div_shift;
105 		config &= BIT(pll->post_div_width) - 1;
128 	struct clk_pll *pll = to_clk_pll(hw);
131 	f = find_freq(pll->freq_tbl, req->rate);
143 	struct clk_pll *pll = to_clk_pll(hw);
149 	f = find_freq(pll->freq_tbl, rate);
153 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
159 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
160 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
161 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
162 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
179 static int wait_for_pll(struct clk_pll *pll)
184 	const char *name = clk_hw_get_name(&pll->clkr.hw);
186 	/* Wait for pll to enable. */
188 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
191 		if (val & BIT(pll->status_bit))
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
224 	regmap_write(regmap, pll->l_reg, config->l);
225 	regmap_write(regmap, pll->m_reg, config->m);
226 	regmap_write(regmap, pll->n_reg, config->n);
242 	regmap_update_bits(regmap, pll->config_reg, mask, val);
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
248 	clk_pll_configure(pll, regmap, config);
250 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
254 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
257 	clk_pll_configure(pll, regmap, config);
259 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
265 	struct clk_pll *pll = to_clk_pll(hw);
269 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
274 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
286 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
291 	ret = wait_for_pll(pll);
296 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
303 	struct clk_pll *pll = to_clk_pll(hw);
309 	f = find_freq(pll->freq_tbl, rate);
313 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
319 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
320 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
321 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);