Lines Matching refs:rate
415 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
421 quotient = rate;
427 return rate;
443 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
449 if (rate >= v->min_freq && rate <= v->max_freq)
537 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
546 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
547 vco = alpha_pll_find_vco(pll, rate);
576 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
579 return __clk_alpha_pll_set_rate(hw, rate, prate,
583 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
586 return __clk_alpha_pll_set_rate(hw, rate, prate,
590 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
598 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
599 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
600 return rate;
605 return clamp(rate, min_freq, max_freq);
622 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
628 quotient = rate;
634 return rate;
658 u64 rate = parent_rate, tmp;
685 return alpha_huayra_pll_calc_rate(rate, l, alpha);
690 rate *= l;
696 rate -= tmp;
700 rate += tmp;
703 return rate;
706 return alpha_huayra_pll_calc_rate(rate, l, alpha);
709 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
715 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
752 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
757 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
941 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
952 return divider_round_rate(hw, rate, prate, table,
957 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
970 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
975 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
982 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1148 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1154 unsigned long rrate, max = rate + PLL_RATE_MARGIN;
1156 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1159 * Due to limited number of bits for fractional rate programming, the
1160 * rounded up rate could be marginally higher than the requested rate.
1162 if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
1163 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1164 clk_hw_get_name(hw), rrate, rate, max);
1210 * Due to a limited number of bits for fractional rate programming, the
1211 * rounded up rate could be marginally higher than the requested rate.
1298 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1303 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1308 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1315 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1336 unsigned long rate, unsigned long *prate)
1340 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1345 unsigned long rate, unsigned long parent_rate)
1361 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1482 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1491 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1494 * Due to a limited number of bits for fractional rate programming, the
1495 * rounded up rate could be marginally higher than the requested rate.
1497 if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
1498 pr_err("Call set rate on the PLL with rounded rates!\n");