Lines Matching refs:pll
12 #include "clk-alpha-pll.h"
161 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
167 const char *name = clk_hw_get_name(&pll->clkr.hw);
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
189 #define wait_for_pll_enable_active(pll) \
190 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
192 #define wait_for_pll_enable_lock(pll) \
193 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
195 #define wait_for_pll_disable(pll) \
196 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
198 #define wait_for_pll_offline(pll) \
199 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
201 #define wait_for_pll_update(pll) \
202 wait_for_pll(pll, PLL_UPDATE, 1, "update")
204 #define wait_for_pll_update_ack_set(pll) \
205 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
207 #define wait_for_pll_update_ack_clear(pll) \
208 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
210 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
215 regmap_write(regmap, PLL_L_VAL(pll), config->l);
216 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
217 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
219 if (pll_has_64bit_config(pll))
220 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
223 if (pll_alpha_width(pll) > 32)
224 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
244 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
246 if (pll->flags & SUPPORTS_FSM_MODE)
247 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
254 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
257 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
263 if (pll->flags & SUPPORTS_OFFLINE_REQ)
266 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
273 return wait_for_pll_enable_active(pll);
279 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
282 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
286 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
287 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
292 ret = wait_for_pll_offline(pll);
298 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
303 wait_for_pll_disable(pll);
309 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
312 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
332 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
336 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
345 return wait_for_pll_enable_active(pll);
352 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
364 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
369 ret = wait_for_pll_enable_lock(pll);
373 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
384 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
387 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
398 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
405 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
443 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
445 const struct pll_vco *v = pll->vco_table;
446 const struct pll_vco *end = v + pll->num_vco;
460 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
461 u32 alpha_width = pll_alpha_width(pll);
463 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
465 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
467 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
469 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
484 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
489 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
492 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
506 ret = wait_for_pll_update_ack_set(pll);
510 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
512 ret = wait_for_pll_update(pll);
517 ret = wait_for_pll_update_ack_clear(pll);
527 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
530 if (!is_enabled(&pll->clkr.hw) ||
531 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
534 return __clk_alpha_pll_update_latch(pll);
541 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
543 u32 l, alpha_width = pll_alpha_width(pll);
547 vco = alpha_pll_find_vco(pll, rate);
548 if (pll->vco_table && !vco) {
549 pr_err("%s: alpha pll not in a valid vco range\n",
554 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
560 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
562 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
565 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
570 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
573 return clk_alpha_pll_update_latch(pll, is_enabled);
593 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
594 u32 l, alpha_width = pll_alpha_width(pll);
599 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
602 min_freq = pll->vco_table[0].min_freq;
603 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
659 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
662 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
663 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
666 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
712 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
717 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
720 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
733 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
736 return wait_for_pll_enable_lock(pll);
739 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
740 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
743 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
746 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
760 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
766 ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
767 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
776 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
778 return trion_pll_is_enabled(pll, pll->clkr.regmap);
783 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
784 struct regmap *regmap = pll->clkr.regmap;
788 ret = regmap_read(regmap, PLL_MODE(pll), &val);
797 return wait_for_pll_enable_active(pll);
801 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
803 ret = wait_for_pll_enable_lock(pll);
808 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
814 return regmap_update_bits(regmap, PLL_MODE(pll),
820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
821 struct regmap *regmap = pll->clkr.regmap;
825 ret = regmap_read(regmap, PLL_MODE(pll), &val);
836 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
841 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
847 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
848 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
854 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
855 u32 l, frac, alpha_width = pll_alpha_width(pll);
857 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
858 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
913 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
916 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
919 ctl &= PLL_POST_DIV_MASK(pll);
944 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
947 if (pll->width == 2)
953 pll->width, CLK_DIVIDER_POWER_OF_TWO);
960 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
963 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
966 ctl &= BIT(pll->width) - 1;
978 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
984 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
985 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1002 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1008 regmap_write(regmap, PLL_L_VAL(pll), config->l);
1011 regmap_write(regmap, PLL_FRAC(pll), config->alpha);
1014 regmap_write(regmap, PLL_CONFIG_CTL(pll),
1018 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
1022 regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1025 regmap_write(regmap, PLL_USER_CTL_U(pll),
1029 regmap_write(regmap, PLL_TEST_CTL(pll),
1033 regmap_write(regmap, PLL_TEST_CTL_U(pll),
1039 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1042 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1045 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1052 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1054 struct regmap *regmap = pll->clkr.regmap;
1056 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1065 return wait_for_pll_enable_active(pll);
1068 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1076 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1080 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1084 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1089 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1093 ret = wait_for_pll_enable_lock(pll);
1097 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1102 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1109 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1111 struct regmap *regmap = pll->clkr.regmap;
1113 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1123 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1128 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1133 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1139 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1140 u32 l, frac, alpha_width = pll_alpha_width(pll);
1142 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1143 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1151 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1152 u32 l, alpha_width = pll_alpha_width(pll);
1168 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1169 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1171 return __clk_alpha_pll_update_latch(pll);
1176 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1180 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1186 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1194 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1196 pr_err("%s: alpha pll not in a valid vco range\n", name);
1200 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1201 pll->vco_table[0].max_freq) * 54, 100);
1217 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1222 pr_err("%s: alpha pll calibration failed\n", name);
1254 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1258 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1262 val >>= pll->post_div_shift;
1263 val &= BIT(pll->width) - 1;
1265 for (i = 0; i < pll->num_post_div; i++) {
1266 if (pll->post_div_table[i].val == val) {
1267 div = pll->post_div_table[i].div;
1278 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1279 struct regmap *regmap = pll->clkr.regmap;
1282 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1284 val >>= pll->post_div_shift;
1285 val &= PLL_POST_DIV_MASK(pll);
1287 for (i = 0; i < pll->num_post_div; i++) {
1288 if (pll->post_div_table[i].val == val) {
1289 div = pll->post_div_table[i].div;
1301 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1303 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1304 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1311 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1312 struct regmap *regmap = pll->clkr.regmap;
1316 for (i = 0; i < pll->num_post_div; i++) {
1317 if (pll->post_div_table[i].div == div) {
1318 val = pll->post_div_table[i].val;
1323 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1324 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1338 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1340 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1341 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1347 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1354 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1362 for (i = 0; i < pll->num_post_div; i++) {
1363 if (pll->post_div_table[i].div == div) {
1364 val = pll->post_div_table[i].val;
1369 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1370 (BIT(pll->width) - 1) << pll->post_div_shift,
1371 val << pll->post_div_shift);
1382 * clk_trion_pll_configure - configure the trion pll
1384 * @pll: clk alpha pll
1386 * @config: configuration to apply for pll
1388 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1392 regmap_write(regmap, PLL_L_VAL(pll), config->l);
1394 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1397 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1400 regmap_write(regmap, PLL_CONFIG_CTL(pll),
1404 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
1408 regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
1412 regmap_write(regmap, PLL_USER_CTL(pll),
1416 regmap_write(regmap, PLL_USER_CTL_U(pll),
1420 regmap_write(regmap, PLL_USER_CTL_U1(pll),
1424 regmap_write(regmap, PLL_TEST_CTL(pll),
1428 regmap_write(regmap, PLL_TEST_CTL_U(pll),
1432 regmap_write(regmap, PLL_TEST_CTL_U1(pll),
1435 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1439 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1442 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1445 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1455 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1460 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val);
1485 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1487 u32 regval, l, alpha_width = pll_alpha_width(pll);
1502 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1503 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1506 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
1513 regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
1520 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
1526 ret = wait_for_pll_enable_lock(pll);