Lines Matching defs:val
164 u32 val;
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
177 if (inverse && !(val & mask))
179 else if ((val & mask) == mask)
213 u32 val, mask;
226 val = config->main_output_mask;
227 val |= config->aux_output_mask;
228 val |= config->aux2_output_mask;
229 val |= config->early_output_mask;
230 val |= config->pre_div_val;
231 val |= config->post_div_val;
232 val |= config->vco_val;
233 val |= config->alpha_en_mask;
234 val |= config->alpha_mode_mask;
244 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
255 u32 val;
257 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
261 val |= PLL_FSM_ENA;
264 val &= ~PLL_OFFLINE_REQ;
266 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
280 u32 val;
282 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
310 u32 val;
312 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
316 return !!(val & mask);
333 u32 val, mask;
336 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
341 if (val & PLL_VOTE_FSM_ENA) {
349 if ((val & mask) == mask)
385 u32 val, mask;
387 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
392 if (val & PLL_VOTE_FSM_ENA) {
567 vco->val << PLL_VCO_SHIFT);
734 /* Ensure that the write above goes to detect L val change. */
785 u32 val;
788 ret = regmap_read(regmap, PLL_MODE(pll), &val);
793 if (val & PLL_VOTE_FSM_ENA) {
822 u32 val;
825 ret = regmap_read(regmap, PLL_MODE(pll), &val);
830 if (val & PLL_VOTE_FSM_ENA) {
1005 u32 val, mask;
1038 val = config->post_div_val;
1039 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1053 u32 val, opmode_val;
1056 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1061 if (val & PLL_VOTE_FSM_ENA) {
1073 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1110 u32 val;
1113 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1118 if (val & PLL_FSM_ENA) {
1180 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1186 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1191 if (val & PLL_RESET_N)
1255 u32 i, div = 1, val;
1258 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1262 val >>= pll->post_div_shift;
1263 val &= BIT(pll->width) - 1;
1266 if (pll->post_div_table[i].val == val) {
1280 u32 i, div = 1, val;
1282 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1284 val >>= pll->post_div_shift;
1285 val &= PLL_POST_DIV_MASK(pll);
1288 if (pll->post_div_table[i].val == val) {
1313 int i, val = 0, div;
1318 val = pll->post_div_table[i].val;
1325 val << PLL_POST_DIV_SHIFT);
1348 int i, val = 0, div, ret;
1354 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1358 if (val & PLL_VOTE_FSM_ENA)
1364 val = pll->post_div_table[i].val;
1371 val << pll->post_div_shift);