Lines Matching refs:val
383 static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val)
385 writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL);
391 u32 val;
393 regmap_read(clk_regmap, clk->reg, &val);
395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy)
413 u32 val;
415 regmap_read(clk_regmap, clk->reg, &val);
417 return ((val & clk->enable_mask) == clk->enable);
429 u32 val, count;
434 regmap_read(clk_regmap, clk->reg, &val);
435 if (val & PLL_CTRL_LOCK)
439 if (val & PLL_CTRL_LOCK)
455 u32 val;
457 regmap_read(clk_regmap, clk->reg, &val);
459 val &= clk->enable | PLL_CTRL_LOCK;
460 if (val == (clk->enable | PLL_CTRL_LOCK))
478 u32 val;
480 regmap_read(clk_regmap, clk->reg, &val);
481 is_direct = val & PLL_CTRL_DIRECT;
482 is_bypass = val & PLL_CTRL_BYPASS;
483 is_feedback = val & PLL_CTRL_FEEDBACK;
485 clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1;
486 clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1;
487 clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1;
518 parent_rate, val, is_direct, is_bypass, is_feedback,
536 u32 val;
542 val = PLL_CTRL_DIRECT;
543 val |= (clk->m_div - 1) << 1;
544 val |= (clk->n_div - 1) << 9;
548 val = PLL_CTRL_BYPASS;
549 val |= (clk->p_div - 1) << 11;
553 val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS;
557 val = PLL_CTRL_FEEDBACK;
558 val |= (clk->m_div - 1) << 1;
559 val |= (clk->n_div - 1) << 9;
560 val |= (clk->p_div - 1) << 11;
564 val = 0x0;
565 val |= (clk->m_div - 1) << 1;
566 val |= (clk->n_div - 1) << 9;
567 val |= (clk->p_div - 1) << 11;
579 return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
716 u32 val;
718 regmap_read(clk_regmap, clk->reg, &val);
719 val &= clk->enable_mask | clk->busy_mask;
721 return (val == (BIT(7) | BIT(0)) ||
722 val == (BIT(8) | BIT(1)));
728 u32 val, hclk_div;
730 regmap_read(clk_regmap, clk->reg, &val);
731 hclk_div = val & clk->busy_mask;
749 u32 val;
754 regmap_read(clk_regmap, clk->reg, &val);
755 val &= clk->enable_mask;
757 return parent_rate / (val >> 7);
771 u32 val, x, y;
773 regmap_read(clk_regmap, clk->reg, &val);
774 x = (val & 0xFF00) >> 8;
775 y = val & 0xFF;
788 { .val = 0, .div = 1 },
789 { .val = 1, .div = 2 },
790 { .val = 2, .div = 4 },
800 u32 val, ctrl_val, count;
810 val = lpc32xx_usb_clk_read(clk);
811 if (clk->busy && (val & clk->busy) == clk->busy) {
818 val |= clk->enable;
819 lpc32xx_usb_clk_write(clk, val);
822 val = lpc32xx_usb_clk_read(clk);
823 if ((val & clk->enable) == clk->enable)
827 if ((val & clk->enable) == clk->enable)
839 u32 val = lpc32xx_usb_clk_read(clk);
841 val &= ~clk->enable;
842 lpc32xx_usb_clk_write(clk, val);
852 u32 ctrl_val, val;
860 val = lpc32xx_usb_clk_read(clk);
862 return ((val & clk->enable) == clk->enable);
888 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask);
890 return regmap_update_bits(clk_regmap, clk->reg, mask, val);
897 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0);
899 regmap_update_bits(clk_regmap, clk->reg, mask, val);
905 u32 val;
908 regmap_read(clk_regmap, clk->reg, &val);
909 is_set = val & BIT(clk->bit_idx);
923 unsigned int val)
928 if (clkt->val == val)
934 unsigned int val, unsigned long flags, u8 width)
937 return val;
939 return _get_table_div(table, val);
940 return val + 1;
947 unsigned int val;
949 regmap_read(clk_regmap, divider->reg, &val);
951 val >>= divider->shift;
952 val &= div_mask(divider->width);
954 return divider_recalc_rate(hw, parent_rate, val, divider->table,
1002 u32 val;
1004 regmap_read(clk_regmap, mux->reg, &val);
1005 val >>= mux->shift;
1006 val &= mux->mask;
1012 if (mux->table[i] == val)
1017 if (val >= num_parents)
1020 return val;
1477 u32 val;
1479 regmap_read(clk_regmap, reg, &val);
1481 if (!(val & div_mask)) {
1482 val &= ~gate;
1483 val |= BIT(__ffs(div_mask));
1486 regmap_update_bits(clk_regmap, reg, gate | div_mask, val);