Lines Matching defs:rate
253 * divider register does not contain information about selected rate.
477 unsigned long rate, cco_rate, ref_rate;
504 rate = cco_rate = ref_rate * clk->m_div;
511 rate /= (1 << clk->p_div);
519 clk->n_div, clk->m_div, (1 << clk->p_div), rate);
529 return rate;
532 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
539 /* Validate PLL clock parameters computed on round rate stage */
575 /* Sanity check that round rate is equal to the requested one */
576 if (new_rate != rate)
582 static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
586 u64 m_i, o = rate, i = *parent_rate, d = (u64)rate << 6;
590 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
592 if (rate > 266500000)
617 if (d == (u64)rate << 6) {
619 clk_hw_get_name(hw), rate);
637 clk_hw_get_name(hw), rate, m, n, p);
640 clk_hw_get_name(hw), rate, m, n, p, o);
645 static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate,
652 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
660 if (rate != 48000000)
690 return rate;
736 * if HCLK clock rate is equal to ARM clock rate
958 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
974 return divider_round_rate(hw, rate, prate, divider->table,
978 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
984 value = divider_get_val(rate, parent_rate, divider->table,
1503 pr_err("invalid clock rate of external 32KHz oscillator\n");
1550 /* Set 48MHz rate of USB PLL clock */