Lines Matching defs:divider
253 * divider register does not contain information about selected rate.
657 * and post-divider must be 4, this slightly simplifies calculation of
658 * USB divider, USB PLL N and M parameters.
663 /* USB divider clock */
674 /* Check if valid USB divider and USB PLL parameters exists */
946 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
949 regmap_read(clk_regmap, divider->reg, &val);
951 val >>= divider->shift;
952 val &= div_mask(divider->width);
954 return divider_recalc_rate(hw, parent_rate, val, divider->table,
955 divider->flags, divider->width);
961 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
965 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
966 regmap_read(clk_regmap, divider->reg, &bestdiv);
967 bestdiv >>= divider->shift;
968 bestdiv &= div_mask(divider->width);
969 bestdiv = _get_div(divider->table, bestdiv, divider->flags,
970 divider->width);
974 return divider_round_rate(hw, rate, prate, divider->table,
975 divider->width, divider->flags);
981 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
984 value = divider_get_val(rate, parent_rate, divider->table,
985 divider->width, divider->flags);
987 return regmap_update_bits(clk_regmap, divider->reg,
988 div_mask(divider->width) << divider->shift,
989 value << divider->shift);
1533 * divider clock is never met in runtime.