Lines Matching refs:SAIF0
34 #define SAIF0 (CLKCTRL + 0x0100)
59 * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
61 * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
62 * SAIF0 clock inputs selected for SAIF1 input clocks.
63 * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
65 * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
93 val = readl_relaxed(SAIF0);
95 writel_relaxed(val, SAIF0);
204 clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
220 clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);