Lines Matching refs:clk_lock
46 static DEFINE_SPINLOCK(clk_lock);
165 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
170 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
174 apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
178 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
182 apbc_base + APBC_KPC, 10, 0, &clk_lock);
186 apbc_base + APBC_RTC, 10, 0, &clk_lock);
190 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
194 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
198 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
202 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
208 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
213 apbc_base + APBC_UART0, 10, 0, &clk_lock);
219 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
224 apbc_base + APBC_UART1, 10, 0, &clk_lock);
230 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
235 apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
241 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
245 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
251 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
255 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
259 apmu_base + APMU_DFC, 0x19b, &clk_lock);
265 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
269 apmu_base + APMU_SDH0, 0x1b, &clk_lock);
275 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
279 apmu_base + APMU_SDH1, 0x1b, &clk_lock);
283 apmu_base + APMU_USB, 0x9, &clk_lock);
287 apmu_base + APMU_USB, 0x12, &clk_lock);
293 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
297 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
303 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
307 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
313 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
317 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
322 10, 5, 0, &clk_lock);
326 apmu_base + APMU_CCIC0, 0x300, &clk_lock);