Lines Matching refs:clk_lock

48 static DEFINE_SPINLOCK(clk_lock);
160 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
165 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
169 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
173 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
177 apbc_base + APBC_KPC, 10, 0, &clk_lock);
181 apbc_base + APBC_RTC, 10, 0, &clk_lock);
185 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
189 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
193 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
197 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
203 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
208 apbc_base + APBC_UART0, 10, 0, &clk_lock);
214 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
219 apbc_base + APBC_UART1, 10, 0, &clk_lock);
225 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
230 apbc_base + APBC_UART2, 10, 0, &clk_lock);
236 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
240 10, 0, &clk_lock);
246 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
250 10, 0, &clk_lock);
256 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
260 10, 0, &clk_lock);
266 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
270 10, 0, &clk_lock);
276 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
280 10, 0, &clk_lock);
284 0x19b, &clk_lock);
290 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
294 0x1b, &clk_lock);
300 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
304 0x1b, &clk_lock);
308 0x9, &clk_lock);
312 0x12, &clk_lock);
318 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
322 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
326 apmu_base + APMU_DISP0, 0x24, &clk_lock);
332 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
336 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
342 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
346 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
351 10, 5, 0, &clk_lock);
355 apmu_base + APMU_CCIC0, 0x300, &clk_lock);