Lines Matching refs:clk_lock
55 static DEFINE_SPINLOCK(clk_lock);
189 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
194 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
198 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
202 apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
206 apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
210 apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
214 apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
218 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
222 apbc_base + APBC_KPC, 10, 0, &clk_lock);
226 apbc_base + APBC_RTC, 10, 0, &clk_lock);
230 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
234 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
238 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
242 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
248 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
253 apbc_base + APBC_UART0, 10, 0, &clk_lock);
259 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
264 apbc_base + APBC_UART1, 10, 0, &clk_lock);
270 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
275 apbc_base + APBC_UART2, 10, 0, &clk_lock);
281 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
286 apbc_base + APBC_UART3, 10, 0, &clk_lock);
292 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
296 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
302 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
306 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
312 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
316 apbc_base + APBC_SSP2, 10, 0, &clk_lock);
322 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
326 apbc_base + APBC_SSP3, 10, 0, &clk_lock);
332 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
337 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
341 0x1b, &clk_lock);
345 0x1b, &clk_lock);
349 0x1b, &clk_lock);
353 0x1b, &clk_lock);
357 0x9, &clk_lock);
363 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
368 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
372 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
376 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
380 apmu_base + APMU_DISP0, 0x1024, &clk_lock);
386 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
391 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
395 apmu_base + APMU_DISP1, 0x1b, &clk_lock);
399 apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
405 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
410 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
414 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
418 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
423 10, 5, 0, &clk_lock);
427 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
433 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
438 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
442 apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
446 apmu_base + APMU_CCIC1, 0x24, &clk_lock);
451 10, 5, 0, &clk_lock);
455 apmu_base + APMU_CCIC1, 0x300, &clk_lock);