Lines Matching refs:clk
12 #include <linux/clk.h>
19 #include <linux/clk/mmp.h>
21 #include "clk.h"
79 struct clk *clk;
80 struct clk *vctcxo;
103 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
104 clk_register_clkdev(clk, "clk32", NULL);
109 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
110 clk_register_clkdev(clk, "pll1", NULL);
112 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
113 clk_register_clkdev(clk, "usb_pll", NULL);
115 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
116 clk_register_clkdev(clk, "pll2", NULL);
118 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
120 clk_register_clkdev(clk, "pll1_2", NULL);
122 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
124 clk_register_clkdev(clk, "pll1_4", NULL);
126 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
128 clk_register_clkdev(clk, "pll1_8", NULL);
130 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
132 clk_register_clkdev(clk, "pll1_16", NULL);
134 clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
136 clk_register_clkdev(clk, "pll1_20", NULL);
138 clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
140 clk_register_clkdev(clk, "pll1_3", NULL);
142 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
144 clk_register_clkdev(clk, "pll1_6", NULL);
146 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
148 clk_register_clkdev(clk, "pll1_12", NULL);
150 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
152 clk_register_clkdev(clk, "pll2_2", NULL);
154 clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
156 clk_register_clkdev(clk, "pll2_4", NULL);
158 clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
160 clk_register_clkdev(clk, "pll2_8", NULL);
162 clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
164 clk_register_clkdev(clk, "pll2_16", NULL);
166 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
168 clk_register_clkdev(clk, "pll2_3", NULL);
170 clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
172 clk_register_clkdev(clk, "pll2_6", NULL);
174 clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
176 clk_register_clkdev(clk, "pll2_12", NULL);
178 clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
180 clk_register_clkdev(clk, "vctcxo_2", NULL);
182 clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
184 clk_register_clkdev(clk, "vctcxo_4", NULL);
186 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
190 clk_set_rate(clk, 14745600);
191 clk_register_clkdev(clk, "uart_pll", NULL);
193 clk = mmp_clk_register_apbc("twsi0", "vctcxo",
195 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
197 clk = mmp_clk_register_apbc("twsi1", "vctcxo",
199 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
201 clk = mmp_clk_register_apbc("twsi2", "vctcxo",
203 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
205 clk = mmp_clk_register_apbc("twsi3", "vctcxo",
207 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
209 clk = mmp_clk_register_apbc("twsi4", "vctcxo",
211 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
213 clk = mmp_clk_register_apbc("twsi5", "vctcxo",
215 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
217 clk = mmp_clk_register_apbc("gpio", "vctcxo",
219 clk_register_clkdev(clk, NULL, "mmp2-gpio");
221 clk = mmp_clk_register_apbc("kpc", "clk32",
223 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
225 clk = mmp_clk_register_apbc("rtc", "clk32",
227 clk_register_clkdev(clk, NULL, "mmp-rtc");
229 clk = mmp_clk_register_apbc("pwm0", "vctcxo",
231 clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
233 clk = mmp_clk_register_apbc("pwm1", "vctcxo",
235 clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
237 clk = mmp_clk_register_apbc("pwm2", "vctcxo",
239 clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
241 clk = mmp_clk_register_apbc("pwm3", "vctcxo",
243 clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
245 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
249 clk_set_parent(clk, vctcxo);
250 clk_register_clkdev(clk, "uart_mux.0", NULL);
252 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
254 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
256 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
260 clk_set_parent(clk, vctcxo);
261 clk_register_clkdev(clk, "uart_mux.1", NULL);
263 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
265 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
267 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
271 clk_set_parent(clk, vctcxo);
272 clk_register_clkdev(clk, "uart_mux.2", NULL);
274 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
276 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
278 clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
282 clk_set_parent(clk, vctcxo);
283 clk_register_clkdev(clk, "uart_mux.3", NULL);
285 clk = mmp_clk_register_apbc("uart3", "uart3_mux",
287 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
289 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
293 clk_register_clkdev(clk, "uart_mux.0", NULL);
295 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
297 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
299 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
303 clk_register_clkdev(clk, "ssp_mux.1", NULL);
305 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
307 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
309 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
313 clk_register_clkdev(clk, "ssp_mux.2", NULL);
315 clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
317 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
319 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
323 clk_register_clkdev(clk, "ssp_mux.3", NULL);
325 clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
327 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
329 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
333 clk_register_clkdev(clk, "sdh_mux", NULL);
335 clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
338 clk_register_clkdev(clk, "sdh_div", NULL);
340 clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
342 clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
344 clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
346 clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
348 clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
350 clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
352 clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
354 clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
356 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
358 clk_register_clkdev(clk, "usb_clk", NULL);
360 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
364 clk_register_clkdev(clk, "disp_mux.0", NULL);
366 clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
369 clk_register_clkdev(clk, "disp_div.0", NULL);
371 clk = mmp_clk_register_apmu("disp0", "disp0_div",
373 clk_register_clkdev(clk, NULL, "mmp-disp.0");
375 clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
377 clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
379 clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
381 clk_register_clkdev(clk, "disp_sphy.0", NULL);
383 clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
387 clk_register_clkdev(clk, "disp_mux.1", NULL);
389 clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
392 clk_register_clkdev(clk, "disp_div.1", NULL);
394 clk = mmp_clk_register_apmu("disp1", "disp1_div",
396 clk_register_clkdev(clk, NULL, "mmp-disp.1");
398 clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
400 clk_register_clkdev(clk, "ccic_arbiter", NULL);
402 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
406 clk_register_clkdev(clk, "ccic_mux.0", NULL);
408 clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
411 clk_register_clkdev(clk, "ccic_div.0", NULL);
413 clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
415 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
417 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
419 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
421 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
424 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
426 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
428 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
430 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
434 clk_register_clkdev(clk, "ccic_mux.1", NULL);
436 clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
439 clk_register_clkdev(clk, "ccic_div.1", NULL);
441 clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
443 clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
445 clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
447 clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
449 clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
452 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
454 clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
456 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");