Lines Matching refs:name
63 .name = "fixed_pll_dco",
80 .name = "fixed_pll",
128 .name = "sys_pll_dco",
147 .name = "sys_pll",
187 .name = "sys1_pll_dco",
206 .name = "sys1_pll",
222 .name = "sys_pll_div16_en",
239 .name = "sys1_pll_div16_en",
256 .name = "sys_pll_div16",
269 .name = "sys1_pll_div16",
282 .name = "fclk_div2_div",
295 .name = "fclk_div2",
319 .name = "fclk_div3_div",
332 .name = "fclk_div3",
360 .name = "cpu_clk_dyn0_sel",
380 .name = "cpu_clk_dyn1_sel",
408 .name = "cpu_clk_dyn0_div",
427 .name = "cpu_clk_dyn0",
446 .name = "cpu_clk_dyn1_div",
463 .name = "cpu_clk_dyn1",
484 .name = "cpu_clk_dyn",
504 .name = "cpu_clk",
524 .name = "cpu_clk",
544 .name = "cpub_clk_dyn0_sel",
571 .name = "cpub_clk_dyn0_div",
590 .name = "cpub_clk_dyn0",
609 .name = "cpub_clk_dyn1_sel",
630 .name = "cpub_clk_dyn1_div",
647 .name = "cpub_clk_dyn1",
668 .name = "cpub_clk_dyn",
688 .name = "cpub_clk",
709 .name = "dsu_clk_dyn0_sel",
729 .name = "dsu_clk_dyn1_sel",
749 .name = "dsu_clk_dyn0_div",
766 .name = "dsu_clk_dyn0",
784 .name = "dsu_clk_dyn1_div",
801 .name = "dsu_clk_dyn1",
819 .name = "dsu_clk_dyn",
837 .name = "dsu_clk_final",
855 .name = "cpu1_clk",
873 .name = "cpu2_clk",
891 .name = "cpu3_clk",
909 .name = "dsu_clk",
1136 .name = "cpu_clk_div16_en",
1155 .name = "cpub_clk_div16_en",
1172 .name = "cpu_clk_div16",
1185 .name = "cpub_clk_div16",
1202 .name = "cpu_clk_apb_div",
1215 .name = "cpu_clk_apb",
1236 .name = "cpu_clk_atb_div",
1249 .name = "cpu_clk_atb",
1270 .name = "cpu_clk_axi_div",
1283 .name = "cpu_clk_axi",
1304 .name = "cpu_clk_trace_div",
1314 .name = "cpu_clk",
1327 .name = "cpu_clk_trace",
1344 .name = "cpub_clk_div2",
1357 .name = "cpub_clk_div3",
1370 .name = "cpub_clk_div4",
1383 .name = "cpub_clk_div5",
1396 .name = "cpub_clk_div6",
1409 .name = "cpub_clk_div7",
1422 .name = "cpub_clk_div8",
1440 .name = "cpub_clk_apb_sel",
1462 .name = "cpub_clk_apb",
1483 .name = "cpub_clk_atb_sel",
1505 .name = "cpub_clk_atb",
1526 .name = "cpub_clk_axi_sel",
1548 .name = "cpub_clk_axi",
1569 .name = "cpub_clk_trace_sel",
1591 .name = "cpub_clk_trace",
1658 .name = "gp0_pll_dco",
1676 .name = "gp0_pll",
1720 .name = "gp1_pll_dco",
1740 .name = "gp1_pll",
1799 .name = "hifi_pll_dco",
1817 .name = "hifi_pll",
1890 .name = "pcie_pll_dco",
1903 .name = "pcie_pll_dco_div2",
1923 .name = "pcie_pll_od",
1937 .name = "pcie_pll_pll",
1981 .name = "hdmi_pll_dco",
2003 .name = "hdmi_pll_od",
2021 .name = "hdmi_pll_od2",
2039 .name = "hdmi_pll",
2053 .name = "fclk_div4_div",
2066 .name = "fclk_div4",
2079 .name = "fclk_div5_div",
2092 .name = "fclk_div5",
2105 .name = "fclk_div7_div",
2118 .name = "fclk_div7",
2131 .name = "fclk_div2p5_div",
2146 .name = "fclk_div2p5",
2159 .name = "mpll_50m_div",
2175 .name = "mpll_50m",
2189 .name = "mpll_prediv",
2229 .name = "mpll0_div",
2244 .name = "mpll0",
2283 .name = "mpll1_div",
2298 .name = "mpll1",
2337 .name = "mpll2_div",
2352 .name = "mpll2",
2391 .name = "mpll3_div",
2406 .name = "mpll3",
2433 .name = "mpeg_clk_sel",
2447 .name = "mpeg_clk_div",
2463 .name = "clk81",
2495 .name = "sd_emmc_a_clk0_sel",
2510 .name = "sd_emmc_a_clk0_div",
2526 .name = "sd_emmc_a_clk0",
2544 .name = "sd_emmc_b_clk0_sel",
2559 .name = "sd_emmc_b_clk0_div",
2575 .name = "sd_emmc_b_clk0",
2593 .name = "sd_emmc_c_clk0_sel",
2608 .name = "sd_emmc_c_clk0_div",
2624 .name = "sd_emmc_c_clk0",
2650 .name = "vid_pll_div",
2670 .name = "vid_pll_sel",
2688 .name = "vid_pll",
2718 .name = "vpu_0_sel",
2733 .name = "vpu_0_div",
2747 .name = "vpu_0",
2762 .name = "vpu_1_sel",
2777 .name = "vpu_1_div",
2791 .name = "vpu_1",
2806 .name = "vpu",
2841 .name = "vdec_1_sel",
2857 .name = "vdec_1_div",
2873 .name = "vdec_1",
2891 .name = "vdec_hevcf_sel",
2907 .name = "vdec_hevcf_div",
2923 .name = "vdec_hevcf",
2941 .name = "vdec_hevc_sel",
2957 .name = "vdec_hevc_div",
2973 .name = "vdec_hevc",
3003 .name = "vapb_0_sel",
3018 .name = "vapb_0_div",
3034 .name = "vapb_0",
3051 .name = "vapb_1_sel",
3066 .name = "vapb_1_div",
3082 .name = "vapb_1",
3099 .name = "vapb_sel",
3120 .name = "vapb",
3146 .name = "vclk_sel",
3161 .name = "vclk2_sel",
3175 .name = "vclk_input",
3189 .name = "vclk2_input",
3204 .name = "vclk_div",
3221 .name = "vclk2_div",
3237 .name = "vclk",
3251 .name = "vclk2",
3265 .name = "vclk_div1",
3279 .name = "vclk_div2_en",
3293 .name = "vclk_div4_en",
3307 .name = "vclk_div6_en",
3321 .name = "vclk_div12_en",
3335 .name = "vclk2_div1",
3349 .name = "vclk2_div2_en",
3363 .name = "vclk2_div4_en",
3377 .name = "vclk2_div6_en",
3391 .name = "vclk2_div12_en",
3403 .name = "vclk_div2",
3416 .name = "vclk_div4",
3429 .name = "vclk_div6",
3442 .name = "vclk_div12",
3455 .name = "vclk2_div2",
3468 .name = "vclk2_div4",
3481 .name = "vclk2_div6",
3494 .name = "vclk2_div12",
3525 .name = "cts_enci_sel",
3541 .name = "cts_encp_sel",
3557 .name = "cts_vdac_sel",
3588 .name = "hdmi_tx_sel",
3602 .name = "cts_enci",
3618 .name = "cts_encp",
3634 .name = "cts_vdac",
3650 .name = "hdmi_tx",
3677 .name = "hdmi_sel",
3692 .name = "hdmi_div",
3706 .name = "hdmi",
3738 .name = "mali_0_sel",
3759 .name = "mali_0_div",
3775 .name = "mali_0",
3792 .name = "mali_1_sel",
3813 .name = "mali_1_div",
3829 .name = "mali_1",
3851 .name = "mali",
3866 .name = "ts_div",
3881 .name = "ts",
3908 .name = "spicc0_sclk_sel",
3922 .name = "spicc0_sclk_div",
3938 .name = "spicc0_sclk",
3955 .name = "spicc1_sclk_sel",
3969 .name = "spicc1_sclk_div",
3985 .name = "spicc1_sclk",
4015 .name = "nna_axi_clk_sel",
4029 .name = "nna_axi_clk_div",
4045 .name = "nna_axi_clk",
4062 .name = "nna_core_clk_sel",
4076 .name = "nna_core_clk_div",
4092 .name = "nna_core_clk",
5377 .name = "g12a-clkc",