clk-pll.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/mediatek/clk-pll.c

Lines Matching refs:pll
57 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
59 	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
65 	int pcwbits = pll->data->pcwbits;
72 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
89 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
93 	if (pll->tuner_en_addr) {
94 		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
95 		writel(r, pll->tuner_en_addr);
96 	} else if (pll->tuner_addr) {
97 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
98 		writel(r, pll->tuner_addr);
102 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
106 	if (pll->tuner_en_addr) {
107 		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
108 		writel(r, pll->tuner_en_addr);
109 	} else if (pll->tuner_addr) {
110 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
111 		writel(r, pll->tuner_addr);
115 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
121 	__mtk_pll_tuner_disable(pll);
124 	val = readl(pll->pd_addr);
125 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
126 	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
129 	if (pll->pd_addr != pll->pcw_addr) {
130 		writel(val, pll->pd_addr);
131 		val = readl(pll->pcw_addr);
135 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
136 			pll->data->pcw_shift);
137 	val |= pcw << pll->data->pcw_shift;
138 	writel(val, pll->pcw_addr);
139 	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
140 	writel(chg, pll->pcw_chg_addr);
141 	if (pll->tuner_addr)
142 		writel(val + 1, pll->tuner_addr);
145 	__mtk_pll_tuner_enable(pll);
152  * @pll:	The pll
159 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
162 	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
163 	const struct mtk_pll_div_table *div_table = pll->data->div_table;
168 	if (freq > pll->data->fmax)
169 		freq = pll->data->fmax;
189 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
190 	_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
199 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
203 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
204 	mtk_pll_set_rate_regs(pll, pcw, postdiv);
212 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
216 	postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
219 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
220 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);
222 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
228 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
232 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
234 	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
239 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
242 	r = readl(pll->pwr_addr) | CON0_PWR_ON;
243 	writel(r, pll->pwr_addr);
246 	r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
247 	writel(r, pll->pwr_addr);
250 	r = readl(pll->base_addr + REG_CON0);
251 	r |= pll->data->en_mask;
252 	writel(r, pll->base_addr + REG_CON0);
254 	__mtk_pll_tuner_enable(pll);
258 	if (pll->data->flags & HAVE_RST_BAR) {
259 		r = readl(pll->base_addr + REG_CON0);
260 		r |= pll->data->rst_bar_mask;
261 		writel(r, pll->base_addr + REG_CON0);
269 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
272 	if (pll->data->flags & HAVE_RST_BAR) {
273 		r = readl(pll->base_addr + REG_CON0);
274 		r &= ~pll->data->rst_bar_mask;
275 		writel(r, pll->base_addr + REG_CON0);
278 	__mtk_pll_tuner_disable(pll);
280 	r = readl(pll->base_addr + REG_CON0);
282 	writel(r, pll->base_addr + REG_CON0);
284 	r = readl(pll->pwr_addr) | CON0_ISO_EN;
285 	writel(r, pll->pwr_addr);
287 	r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
288 	writel(r, pll->pwr_addr);
303 	struct mtk_clk_pll *pll;
308 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
309 	if (!pll)
312 	pll->base_addr = base + data->reg;
313 	pll->pwr_addr = base + data->pwr_reg;
314 	pll->pd_addr = base + data->pd_reg;
315 	pll->pcw_addr = base + data->pcw_reg;
317 		pll->pcw_chg_addr = base + data->pcw_chg_reg;
319 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;
321 		pll->tuner_addr = base + data->tuner_reg;
323 		pll->tuner_en_addr = base + data->tuner_en_reg;
324 	pll->hw.init = &init;
325 	pll->data = data;
336 	clk = clk_register(NULL, &pll->hw);
339 		kfree(pll);
358 		const struct mtk_pll_data *pll = &plls[i];
360 		clk = mtk_clk_register_pll(pll, base);
364 					pll->name, PTR_ERR(clk));
368 		clk_data->clks[pll->id] = clk;