Lines Matching defs:GATE_PERI0
661 #define GATE_PERI0(_id, _name, _parent, _shift) { \
681 GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
682 GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
683 GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
684 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
685 GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
686 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
687 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
688 GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
689 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
690 GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
691 GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
692 GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
693 GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
694 GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
695 GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
696 GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
697 GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
698 GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
699 GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
700 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
701 GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
702 GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
703 GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
704 GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
705 GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
706 GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
707 GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
708 GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
709 GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
710 GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
711 GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
712 GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),