Lines Matching refs:GATE_ICG0
424 #define GATE_ICG0(_id, _name, _parent, _shift) { \
464 GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
465 GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
466 GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
467 GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
468 GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
469 GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
470 GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
471 GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
472 GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
473 GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
474 GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
475 GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
476 GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
477 GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
478 GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
479 GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
480 GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
481 GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
482 GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
483 GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
484 GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
485 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
486 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
487 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
488 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
489 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
490 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
491 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
492 GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
493 GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),