Lines Matching refs:pll_info
85 const struct ingenic_cgu_pll_info *pll_info;
91 pll_info = &clk_info->pll;
93 ctl = readl(cgu->base + pll_info->reg);
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
96 m += pll_info->m_offset;
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
98 n += pll_info->n_offset;
99 od_enc = ctl >> pll_info->od_shift;
100 od_enc &= GENMASK(pll_info->od_bits - 1, 0);
102 ctl = readl(cgu->base + pll_info->bypass_reg);
104 bypass = !pll_info->no_bypass_bit &&
105 !!(ctl & BIT(pll_info->bypass_bit));
110 for (od = 0; od < pll_info->od_max; od++) {
111 if (pll_info->od_encoding[od] == od_enc)
114 BUG_ON(od == pll_info->od_max);
117 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
126 const struct ingenic_cgu_pll_info *pll_info;
129 pll_info = &clk_info->pll;
138 n = max_t(unsigned, n, pll_info->n_offset);
142 m = max_t(unsigned, m, pll_info->m_offset);
151 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
166 const struct ingenic_cgu_pll_info *pll_info)
170 return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
171 ctl & BIT(pll_info->stable_bit),
182 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
195 ctl = readl(cgu->base + pll_info->reg);
197 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);
198 ctl |= (m - pll_info->m_offset) << pll_info->m_shift;
200 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
201 ctl |= (n - pll_info->n_offset) << pll_info->n_shift;
203 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
204 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
206 writel(ctl, cgu->base + pll_info->reg);
209 if (ctl & BIT(pll_info->enable_bit))
210 ret = ingenic_pll_check_stable(cgu, pll_info);
222 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
228 ctl = readl(cgu->base + pll_info->bypass_reg);
230 ctl &= ~BIT(pll_info->bypass_bit);
232 writel(ctl, cgu->base + pll_info->bypass_reg);
234 ctl = readl(cgu->base + pll_info->reg);
236 ctl |= BIT(pll_info->enable_bit);
238 writel(ctl, cgu->base + pll_info->reg);
240 ret = ingenic_pll_check_stable(cgu, pll_info);
251 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
256 ctl = readl(cgu->base + pll_info->reg);
258 ctl &= ~BIT(pll_info->enable_bit);
260 writel(ctl, cgu->base + pll_info->reg);
269 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
272 ctl = readl(cgu->base + pll_info->reg);
274 return !!(ctl & BIT(pll_info->enable_bit));