Lines Matching refs:cgu
23 #include "cgu.h"
30 return &clk->cgu->clock_info[clk->idx];
35 * @cgu: reference to the CGU whose registers should be read
39 * caller must hold cgu->lock.
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit))
53 * @cgu: reference to the CGU whose registers should be modified
59 * The caller must hold cgu->lock.
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu,
65 u32 clkgr = readl(cgu->base + info->reg);
72 writel(clkgr, cgu->base + info->reg);
84 struct ingenic_cgu *cgu = ingenic_clk->cgu;
93 ctl = readl(cgu->base + pll_info->reg);
102 ctl = readl(cgu->base + pll_info->bypass_reg);
165 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu,
170 return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
180 struct ingenic_cgu *cgu = ingenic_clk->cgu;
191 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n",
194 spin_lock_irqsave(&cgu->lock, flags);
195 ctl = readl(cgu->base + pll_info->reg);
206 writel(ctl, cgu->base + pll_info->reg);
210 ret = ingenic_pll_check_stable(cgu, pll_info);
212 spin_unlock_irqrestore(&cgu->lock, flags);
220 struct ingenic_cgu *cgu = ingenic_clk->cgu;
227 spin_lock_irqsave(&cgu->lock, flags);
228 ctl = readl(cgu->base + pll_info->bypass_reg);
232 writel(ctl, cgu->base + pll_info->bypass_reg);
234 ctl = readl(cgu->base + pll_info->reg);
238 writel(ctl, cgu->base + pll_info->reg);
240 ret = ingenic_pll_check_stable(cgu, pll_info);
241 spin_unlock_irqrestore(&cgu->lock, flags);
249 struct ingenic_cgu *cgu = ingenic_clk->cgu;
255 spin_lock_irqsave(&cgu->lock, flags);
256 ctl = readl(cgu->base + pll_info->reg);
260 writel(ctl, cgu->base + pll_info->reg);
261 spin_unlock_irqrestore(&cgu->lock, flags);
267 struct ingenic_cgu *cgu = ingenic_clk->cgu;
272 ctl = readl(cgu->base + pll_info->reg);
295 struct ingenic_cgu *cgu = ingenic_clk->cgu;
300 reg = readl(cgu->base + clk_info->mux.reg);
321 struct ingenic_cgu *cgu = ingenic_clk->cgu;
349 spin_lock_irqsave(&cgu->lock, flags);
352 reg = readl(cgu->base + clk_info->mux.reg);
355 writel(reg, cgu->base + clk_info->mux.reg);
357 spin_unlock_irqrestore(&cgu->lock, flags);
369 struct ingenic_cgu *cgu = ingenic_clk->cgu;
374 div_reg = readl(cgu->base + clk_info->div.reg);
460 static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,
465 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,
476 struct ingenic_cgu *cgu = ingenic_clk->cgu;
494 spin_lock_irqsave(&cgu->lock, flags);
495 reg = readl(cgu->base + clk_info->div.reg);
511 writel(reg, cgu->base + clk_info->div.reg);
515 ret = ingenic_clk_check_stable(cgu, clk_info);
517 spin_unlock_irqrestore(&cgu->lock, flags);
528 struct ingenic_cgu *cgu = ingenic_clk->cgu;
533 spin_lock_irqsave(&cgu->lock, flags);
534 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
535 spin_unlock_irqrestore(&cgu->lock, flags);
548 struct ingenic_cgu *cgu = ingenic_clk->cgu;
553 spin_lock_irqsave(&cgu->lock, flags);
554 ingenic_cgu_gate_set(cgu, &clk_info->gate, true);
555 spin_unlock_irqrestore(&cgu->lock, flags);
563 struct ingenic_cgu *cgu = ingenic_clk->cgu;
567 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
589 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
591 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
602 clk = of_clk_get_by_name(cgu->np, clk_info->name);
614 cgu->clocks.clks[idx] = clk;
631 ingenic_clk->cgu = cgu;
659 parent = cgu->clocks.clks[clk_info->parents[i]];
670 parent = cgu->clocks.clks[clk_info->parents[0]];
725 cgu->clocks.clks[idx] = clk;
736 struct ingenic_cgu *cgu;
738 cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);
739 if (!cgu)
742 cgu->base = of_iomap(np, 0);
743 if (!cgu->base) {
748 cgu->np = np;
749 cgu->clock_info = clock_info;
750 cgu->clocks.clk_num = num_clocks;
752 spin_lock_init(&cgu->lock);
754 return cgu;
757 kfree(cgu);
762 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)
767 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),
769 if (!cgu->clocks.clks) {
774 for (i = 0; i < cgu->clocks.clk_num; i++) {
775 err = ingenic_register_clock(cgu, i);
780 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,
781 &cgu->clocks);
788 for (i = 0; i < cgu->clocks.clk_num; i++) {
789 if (!cgu->clocks.clks[i])
791 if (cgu->clock_info[i].type & CGU_CLK_EXT)
792 clk_put(cgu->clocks.clks[i]);
794 clk_unregister(cgu->clocks.clks[i]);
796 kfree(cgu->clocks.clks);