Lines Matching defs:clk_info
83 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
90 BUG_ON(clk_info->type != CGU_CLK_PLL);
91 pll_info = &clk_info->pll;
122 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
129 pll_info = &clk_info->pll;
137 n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
141 m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
160 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
162 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL);
181 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
182 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
188 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
192 clk_info->name, req_rate, rate);
221 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
222 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
250 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
251 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
268 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
269 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
294 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
299 if (clk_info->type & CGU_CLK_MUX) {
300 reg = readl(cgu->base + clk_info->mux.reg);
301 hw_idx = (reg >> clk_info->mux.shift) &
302 GENMASK(clk_info->mux.bits - 1, 0);
309 if (clk_info->parents[i] != -1)
320 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
326 if (clk_info->type & CGU_CLK_MUX) {
331 * clk_info->parents which does not equal -1.
334 num_poss = 1 << clk_info->mux.bits;
336 if (clk_info->parents[hw_idx] == -1)
346 mask = GENMASK(clk_info->mux.bits - 1, 0);
347 mask <<= clk_info->mux.shift;
352 reg = readl(cgu->base + clk_info->mux.reg);
354 reg |= hw_idx << clk_info->mux.shift;
355 writel(reg, cgu->base + clk_info->mux.reg);
368 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
373 if (clk_info->type & CGU_CLK_DIV) {
374 div_reg = readl(cgu->base + clk_info->div.reg);
375 div = (div_reg >> clk_info->div.shift) &
376 GENMASK(clk_info->div.bits - 1, 0);
378 if (clk_info->div.div_table)
379 div = clk_info->div.div_table[div];
381 div = (div + 1) * clk_info->div.div;
384 } else if (clk_info->type & CGU_CLK_FIXDIV) {
385 rate /= clk_info->fixdiv.div;
392 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
397 for (i = 0; i < (1 << clk_info->div.bits)
398 && clk_info->div.div_table[i]; i++) {
399 if (clk_info->div.div_table[i] >= div &&
400 clk_info->div.div_table[i] < best) {
401 best = clk_info->div.div_table[i];
413 ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
421 if (clk_info->div.div_table) {
422 hw_div = ingenic_clk_calc_hw_div(clk_info, div);
424 return clk_info->div.div_table[hw_div];
428 div = clamp_t(unsigned int, div, clk_info->div.div,
429 clk_info->div.div << clk_info->div.bits);
436 div = DIV_ROUND_UP(div, clk_info->div.div);
437 div *= clk_info->div.div;
447 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
450 if (clk_info->type & CGU_CLK_DIV)
451 div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
452 else if (clk_info->type & CGU_CLK_FIXDIV)
453 div = clk_info->fixdiv.div;
461 const struct ingenic_cgu_clk_info *clk_info)
465 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,
466 !(reg & BIT(clk_info->div.busy_bit)),
475 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
482 if (clk_info->type & CGU_CLK_DIV) {
483 div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
489 if (clk_info->div.div_table)
490 hw_div = ingenic_clk_calc_hw_div(clk_info, div);
492 hw_div = ((div / clk_info->div.div) - 1);
495 reg = readl(cgu->base + clk_info->div.reg);
498 mask = GENMASK(clk_info->div.bits - 1, 0);
499 reg &= ~(mask << clk_info->div.shift);
500 reg |= hw_div << clk_info->div.shift;
503 if (clk_info->div.stop_bit != -1)
504 reg &= ~BIT(clk_info->div.stop_bit);
507 if (clk_info->div.ce_bit != -1)
508 reg |= BIT(clk_info->div.ce_bit);
511 writel(reg, cgu->base + clk_info->div.reg);
514 if (clk_info->div.busy_bit != -1)
515 ret = ingenic_clk_check_stable(cgu, clk_info);
527 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
531 if (clk_info->type & CGU_CLK_GATE) {
534 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
537 if (clk_info->gate.delay_us)
538 udelay(clk_info->gate.delay_us);
547 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
551 if (clk_info->type & CGU_CLK_GATE) {
554 ingenic_cgu_gate_set(cgu, &clk_info->gate, true);
562 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
566 if (clk_info->type & CGU_CLK_GATE)
567 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
591 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
599 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names));
601 if (clk_info->type == CGU_CLK_EXT) {
602 clk = of_clk_get_by_name(cgu->np, clk_info->name);
605 __func__, clk_info->name);
609 err = clk_register_clkdev(clk, clk_info->name, NULL);
618 if (!clk_info->type) {
620 clk_info->name);
634 clk_init.name = clk_info->name;
638 caps = clk_info->type;
651 num_possible = 1 << clk_info->mux.bits;
653 num_possible = ARRAY_SIZE(clk_info->parents);
656 if (clk_info->parents[i] == -1)
659 parent = cgu->clocks.clks[clk_info->parents[i]];
668 BUG_ON(clk_info->parents[0] == -1);
670 parent = cgu->clocks.clks[clk_info->parents[0]];
675 clk_init.ops = clk_info->custom.clk_ops;
716 clk_info->name);
721 err = clk_register_clkdev(clk, clk_info->name, NULL);