Lines Matching refs:name
67 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
68 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
70 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
72 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
75 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
76 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
78 #define imx_clk_pfd(name, parent_name, reg, idx) \
79 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
81 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
84 #define imx_clk_fixed(name, rate) \
85 to_clk(imx_clk_hw_fixed(name, rate))
87 #define imx_clk_fixed_factor(name, parent, mult, div) \
88 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
90 #define imx_clk_divider(name, parent, reg, shift, width) \
91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
93 #define imx_clk_divider2(name, parent, reg, shift, width) \
94 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
96 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
97 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
99 #define imx_clk_gate(name, parent, reg, shift) \
100 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
102 #define imx_clk_gate_dis(name, parent, reg, shift) \
103 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
105 #define imx_clk_gate2(name, parent, reg, shift) \
106 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
108 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
109 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
111 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
112 to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
114 #define imx_clk_gate3(name, parent, reg, shift) \
115 to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
117 #define imx_clk_gate4(name, parent, reg, shift) \
118 to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
120 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
121 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
123 #define imx_clk_pllv1(type, name, parent, base) \
124 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
126 #define imx_clk_pllv2(name, parent, base) \
127 to_clk(imx_clk_hw_pllv2(name, parent, base))
129 #define imx_clk_frac_pll(name, parent_name, base) \
130 to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
132 #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
134 to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
137 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
140 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
141 to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
143 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
147 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
150 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
153 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
156 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
176 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
196 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
199 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
206 const char *name, unsigned long rate);
209 const char *name, unsigned long rate);
212 const char *name);
214 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
217 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
220 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
223 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
227 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
231 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
237 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
241 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
252 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
256 return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);
259 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
261 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
264 static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg,
268 return clk_hw_register_mux(NULL, name, parents, num_parents,
273 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
276 return clk_hw_register_fixed_factor(NULL, name, parent,
280 static inline struct clk_hw *imx_clk_hw_divider(const char *name,
285 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
289 static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
294 return clk_hw_register_divider(NULL, name, parent, flags,
298 static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent,
301 return clk_hw_register_divider(NULL, name, parent,
306 static inline struct clk *imx_clk_divider2_flags(const char *name,
310 return clk_register_divider(NULL, name, parent,
315 static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
318 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
322 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
325 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
329 static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,
332 return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
336 static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
339 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
343 static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent,
346 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
350 static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent,
353 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
357 static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
360 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
364 static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
368 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
372 static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
376 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
382 const char *name, const char *parent,
386 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
392 static inline struct clk *imx_clk_gate2_cgr(const char *name,
395 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
399 static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
402 return clk_hw_register_gate(NULL, name, parent,
407 static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name,
411 return clk_hw_register_gate(NULL, name, parent,
416 #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
417 to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
419 static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
422 return clk_hw_register_gate2(NULL, name, parent,
427 static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
431 return clk_hw_register_gate2(NULL, name, parent,
436 #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
437 to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
439 static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
443 return clk_hw_register_mux(NULL, name, parents, num_parents,
449 const char *name, void __iomem *reg, u8 shift,
452 return clk_hw_register_mux(dev, name, parents, num_parents,
457 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
461 return clk_register_mux(NULL, name, parents, num_parents,
466 static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
471 return clk_hw_register_mux(NULL, name, parents, num_parents,
477 static inline struct clk *imx_clk_mux_flags(const char *name,
482 return clk_register_mux(NULL, name, parents, num_parents,
487 static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name,
492 return clk_hw_register_mux(NULL, name, parents, num_parents,
497 static inline struct clk *imx_clk_mux2_flags(const char *name,
502 return clk_register_mux(NULL, name, parents, num_parents,
507 static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
514 return clk_hw_register_mux(NULL, name, parents, num_parents,
520 const char *name,
527 return clk_hw_register_mux(dev, name, parents, num_parents,
532 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
540 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
547 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
548 imx8m_clk_hw_composite_flags(name, parent_names, \
553 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
554 imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
558 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \
559 imx8m_clk_hw_composite_flags(name, parent_names, \
564 #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
566 to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
569 #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
570 imx8m_clk_hw_composite_flags(name, parent_names, \
574 #define __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, flags) \
575 imx8m_clk_hw_composite_flags(name, parent_names, \
579 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
580 __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, 0)
582 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
583 __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)
585 #define __imx8m_clk_composite(name, parent_names, reg, flags) \
586 to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
588 #define imx8m_clk_hw_composite(name, parent_names, reg) \
589 __imx8m_clk_hw_composite(name, parent_names, reg, 0)
591 #define imx8m_clk_composite(name, parent_names, reg) \
592 __imx8m_clk_composite(name, parent_names, reg, 0)
594 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
595 __imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
597 #define imx8m_clk_composite_critical(name, parent_names, reg) \
598 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
600 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,