Lines Matching refs:parent
81 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
87 #define imx_clk_fixed_factor(name, parent, mult, div) \
88 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
90 #define imx_clk_divider(name, parent, reg, shift, width) \
91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
93 #define imx_clk_divider2(name, parent, reg, shift, width) \
94 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
96 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
97 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
99 #define imx_clk_gate(name, parent, reg, shift) \
100 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
102 #define imx_clk_gate_dis(name, parent, reg, shift) \
103 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
105 #define imx_clk_gate2(name, parent, reg, shift) \
106 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
108 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
109 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
111 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
112 to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
114 #define imx_clk_gate3(name, parent, reg, shift) \
115 to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
117 #define imx_clk_gate4(name, parent, reg, shift) \
118 to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
123 #define imx_clk_pllv1(type, name, parent, base) \
124 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
126 #define imx_clk_pllv2(name, parent, base) \
127 to_clk(imx_clk_hw_pllv2(name, parent, base))
132 #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
134 to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
148 const char *parent, void __iomem *base);
150 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
159 u8 parent, u8 bypass1, u8 bypass2,
214 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
237 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
274 const char *parent, unsigned int mult, unsigned int div)
276 return clk_hw_register_fixed_factor(NULL, name, parent,
281 const char *parent,
285 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
290 const char *parent,
294 return clk_hw_register_divider(NULL, name, parent, flags,
298 static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent,
301 return clk_hw_register_divider(NULL, name, parent,
307 const char *parent, void __iomem *reg, u8 shift, u8 width,
310 return clk_register_divider(NULL, name, parent,
315 static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
318 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
322 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
325 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
330 const char *parent, void __iomem *reg, u8 shift)
332 return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
336 static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
339 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
343 static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent,
346 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
350 static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent,
353 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
357 static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
360 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
365 const char *parent, void __iomem *reg, u8 shift,
368 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
373 const char *parent, void __iomem *reg, u8 shift,
376 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
382 const char *name, const char *parent,
386 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
393 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
395 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
399 static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
402 return clk_hw_register_gate(NULL, name, parent,
408 const char *parent, void __iomem *reg, u8 shift,
411 return clk_hw_register_gate(NULL, name, parent,
416 #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
417 to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
419 static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
422 return clk_hw_register_gate2(NULL, name, parent,
428 const char *parent, void __iomem *reg, u8 shift,
431 return clk_hw_register_gate2(NULL, name, parent,
436 #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
437 to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))