Lines Matching defs:to_clk
68 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
72 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
76 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
79 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
85 to_clk(imx_clk_hw_fixed(name, rate))
88 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
94 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
97 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
100 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
103 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
106 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
109 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
112 to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
115 to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
118 to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
121 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
124 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
127 to_clk(imx_clk_hw_pllv2(name, parent, base))
130 to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
134 to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
141 to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
245 static inline struct clk *to_clk(struct clk_hw *hw)
417 to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
437 to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
566 to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
586 to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))