Lines Matching refs:val
100 u32 val;
102 val = readl_relaxed(pll->base + PLL_CFG0);
105 if (!(val & SSCG_PLL_BYPASS2_MASK))
106 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
300 u32 val = readl_relaxed(pll->base + PLL_CFG0);
302 return (val & PLL_PD_MASK) ? 0 : 1;
308 u32 val;
310 val = readl_relaxed(pll->base + PLL_CFG0);
311 val &= ~PLL_PD_MASK;
312 writel_relaxed(val, pll->base + PLL_CFG0);
320 u32 val;
322 val = readl_relaxed(pll->base + PLL_CFG0);
323 val |= PLL_PD_MASK;
324 writel_relaxed(val, pll->base + PLL_CFG0);
331 u32 val, divr1, divf1, divr2, divf2, divq;
334 val = readl_relaxed(pll->base + PLL_CFG2);
335 divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
336 divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
337 divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
338 divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
339 divq = FIELD_GET(PLL_DIVQ_MASK, val);
343 val = readl(pll->base + PLL_CFG0);
344 if (val & SSCG_PLL_BYPASS2_MASK) {
346 } else if (val & SSCG_PLL_BYPASS1_MASK) {
363 u32 val;
366 val = readl(pll->base + PLL_CFG0);
367 val &= ~SSCG_PLL_BYPASS_MASK;
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
369 writel(val, pll->base + PLL_CFG0);
371 val = readl_relaxed(pll->base + PLL_CFG2);
372 val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
373 val &= ~(PLL_DIVR1_MASK | PLL_DIVR2_MASK | PLL_DIVQ_MASK);
374 val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1);
375 val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2);
376 val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1);
377 val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2);
378 val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq);
379 writel_relaxed(val, pll->base + PLL_CFG2);
387 u32 val;
390 val = readl(pll->base + PLL_CFG0);
391 if (val & SSCG_PLL_BYPASS2_MASK)
393 else if (val & SSCG_PLL_BYPASS1_MASK)
401 u32 val;
403 val = readl(pll->base + PLL_CFG0);
404 val &= ~SSCG_PLL_BYPASS_MASK;
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
406 writel(val, pll->base + PLL_CFG0);