clk-pllv3.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/imx/clk-pllv3.c

Lines Matching refs:pll
35  * @power_bit:	 pll power bit mask
60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
62 	u32 val = readl_relaxed(pll->base) & pll->power_bit;
64 	/* No need to wait for lock when pll is not powered up */
65 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
68 	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
74 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
77 	val = readl_relaxed(pll->base);
78 	if (pll->powerup_set)
79 		val |= pll->power_bit;
81 		val &= ~pll->power_bit;
82 	writel_relaxed(val, pll->base);
84 	return clk_pllv3_wait_lock(pll);
89 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
92 	val = readl_relaxed(pll->base);
93 	if (pll->powerup_set)
94 		val &= ~pll->power_bit;
96 		val |= pll->power_bit;
97 	writel_relaxed(val, pll->base);
102 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
104 	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
113 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
114 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
131 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
141 	val = readl_relaxed(pll->base);
142 	val &= ~(pll->div_mask << pll->div_shift);
143 	val |= (div << pll->div_shift);
144 	writel_relaxed(val, pll->base);
146 	return clk_pllv3_wait_lock(pll);
161 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
162 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
187 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
196 	val = readl_relaxed(pll->base);
197 	val &= ~pll->div_mask;
199 	writel_relaxed(val, pll->base);
201 	return clk_pllv3_wait_lock(pll);
216 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
217 	u32 mfn = readl_relaxed(pll->base + pll->num_offset);
218 	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
219 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
263 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
283 	val = readl_relaxed(pll->base);
284 	val &= ~pll->div_mask;
286 	writel_relaxed(val, pll->base);
287 	writel_relaxed(mfn, pll->base + pll->num_offset);
288 	writel_relaxed(mfd, pll->base + pll->denom_offset);
290 	return clk_pllv3_wait_lock(pll);
347 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
350 	mf.mfn = readl_relaxed(pll->base + pll->num_offset);
351 	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
352 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
368 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
373 	val = readl_relaxed(pll->base);
375 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */
377 		val |= pll->div_mask;	/* set bit for mfi=22 */
378 	writel_relaxed(val, pll->base);
380 	writel_relaxed(mf.mfn, pll->base + pll->num_offset);
381 	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
383 	return clk_pllv3_wait_lock(pll);
398 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
400 	return pll->ref_clock;
414 	struct clk_pllv3 *pll;
420 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
421 	if (!pll)
424 	pll->power_bit = BM_PLL_POWER;
425 	pll->num_offset = PLL_NUM_OFFSET;
426 	pll->denom_offset = PLL_DENOM_OFFSET;
434 		pll->num_offset = PLL_VF610_NUM_OFFSET;
435 		pll->denom_offset = PLL_VF610_DENOM_OFFSET;
438 		pll->div_shift = 1;
442 		pll->powerup_set = true;
445 		pll->num_offset = PLL_IMX7_NUM_OFFSET;
446 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
452 		pll->power_bit = IMX7_ENET_PLL_POWER;
453 		pll->ref_clock = 1000000000;
457 		pll->ref_clock = 500000000;
461 		pll->power_bit = IMX7_DDR_PLL_POWER;
462 		pll->num_offset = PLL_IMX7_NUM_OFFSET;
463 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
469 	pll->base = base;
470 	pll->div_mask = div_mask;
478 	pll->hw.init = &init;
479 	hw = &pll->hw;
483 		kfree(pll);