Lines Matching refs:base
99 * @base: Base memory address
106 void __iomem *base;
122 mult = readl(pll->base + PLLM) & pll->pllm_mask;
188 writel(mult - 1, pll->base + PLLM);
214 mult = readl(pll->base + PLLM) & pll->pllm_mask;
290 void __iomem *base;
314 ctrl = readl(pll->base + PLLCTL);
319 writel(ctrl, pll->base + PLLCTL);
325 writel(ctrl, pll->base + PLLCTL);
331 writel(ctrl, pll->base + PLLCTL);
337 writel(ctrl, pll->base + PLLCTL);
352 * @base: The PLL's memory region
369 void __iomem *base,
419 parent_name, base + PREDIV, fixed, flags);
459 pllout->base = base;
485 parent_name, base + POSTDIV, fixed, flags);
509 pllen->base = base;
541 * @base: The PLL memory region
545 void __iomem *base)
547 return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN,
555 * @base: The PLL memory region
559 void __iomem *base)
561 return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
570 * @base: The PLL memory region
575 void __iomem *base)
588 mux->reg = base + OCSEL;
598 gate->reg = base + CKEN;
607 divider->reg = base + OSCDIV;
612 oscdiv = readl(base + OSCDIV);
614 writel(oscdiv, base + OSCDIV);
651 pllcmd = readl(pll->base + PLLCMD);
653 writel(pllcmd, pll->base + PLLCMD);
658 pllstat = readl(pll->base + PLLSTAT);
674 * @base: The PLL memory region
679 void __iomem *base)
699 gate->reg = base + reg;
708 divider->reg = base + reg;
750 void __iomem *base,
762 clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
800 clk = davinci_pll_sysclk_register(dev, *div_info, base);
817 clk = davinci_pll_auxclk_register(dev, child_name, base);
829 clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
904 typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
913 void __iomem *base;
932 base = devm_platform_ioremap_resource(pdev, 0);
933 if (IS_ERR(base))
934 return PTR_ERR(base);
936 return pll_init(dev, base, pdata->cfgchip);
1004 regset->base = pll->base;