clk-xgene.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/clk-xgene.c

Lines Matching defs:pclk
446 	struct xgene_clk *pclk = to_xgene_clk(hw);
450 	if (pclk->lock)
451 		spin_lock_irqsave(pclk->lock, flags);
453 	if (pclk->param.csr_reg) {
456 		data = xgene_clk_read(pclk->param.csr_reg +
457 					pclk->param.reg_clk_offset);
458 		data |= pclk->param.reg_clk_mask;
459 		xgene_clk_write(data, pclk->param.csr_reg +
460 					pclk->param.reg_clk_offset);
463 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
467 		data = xgene_clk_read(pclk->param.csr_reg +
468 					pclk->param.reg_csr_offset);
469 		data &= ~pclk->param.reg_csr_mask;
470 		xgene_clk_write(data, pclk->param.csr_reg +
471 					pclk->param.reg_csr_offset);
474 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
478 	if (pclk->lock)
479 		spin_unlock_irqrestore(pclk->lock, flags);
486 	struct xgene_clk *pclk = to_xgene_clk(hw);
490 	if (pclk->lock)
491 		spin_lock_irqsave(pclk->lock, flags);
493 	if (pclk->param.csr_reg) {
496 		data = xgene_clk_read(pclk->param.csr_reg +
497 					pclk->param.reg_csr_offset);
498 		data |= pclk->param.reg_csr_mask;
499 		xgene_clk_write(data, pclk->param.csr_reg +
500 					pclk->param.reg_csr_offset);
503 		data = xgene_clk_read(pclk->param.csr_reg +
504 					pclk->param.reg_clk_offset);
505 		data &= ~pclk->param.reg_clk_mask;
506 		xgene_clk_write(data, pclk->param.csr_reg +
507 					pclk->param.reg_clk_offset);
510 	if (pclk->lock)
511 		spin_unlock_irqrestore(pclk->lock, flags);
516 	struct xgene_clk *pclk = to_xgene_clk(hw);
519 	if (pclk->param.csr_reg) {
521 		data = xgene_clk_read(pclk->param.csr_reg +
522 					pclk->param.reg_clk_offset);
524 			data & pclk->param.reg_clk_mask ? "enabled" :
528 	if (!pclk->param.csr_reg)
530 	return data & pclk->param.reg_clk_mask ? 1 : 0;
536 	struct xgene_clk *pclk = to_xgene_clk(hw);
539 	if (pclk->param.divider_reg) {
540 		data = xgene_clk_read(pclk->param.divider_reg +
541 					pclk->param.reg_divider_offset);
542 		data >>= pclk->param.reg_divider_shift;
543 		data &= (1 << pclk->param.reg_divider_width) - 1;
560 	struct xgene_clk *pclk = to_xgene_clk(hw);
566 	if (pclk->lock)
567 		spin_lock_irqsave(pclk->lock, flags);
569 	if (pclk->param.divider_reg) {
574 		divider &= (1 << pclk->param.reg_divider_width) - 1;
575 		divider <<= pclk->param.reg_divider_shift;
578 		data = xgene_clk_read(pclk->param.divider_reg +
579 				pclk->param.reg_divider_offset);
580 		data &= ~(((1 << pclk->param.reg_divider_width) - 1)
581 				<< pclk->param.reg_divider_shift);
583 		xgene_clk_write(data, pclk->param.divider_reg +
584 					pclk->param.reg_divider_offset);
591 	if (pclk->lock)
592 		spin_unlock_irqrestore(pclk->lock, flags);
600 	struct xgene_clk *pclk = to_xgene_clk(hw);
604 	if (pclk->param.divider_reg) {