Lines Matching refs:val
458 u16 val;
464 val = readw(sclk->res_reg);
465 val |= BIT(sclk->res_bit);
466 writew(val, sclk->res_reg);
474 u16 val;
480 val = readw(sclk->res_reg);
481 val &= ~BIT(sclk->res_bit);
482 writew(val, sclk->res_reg);
543 u16 val;
549 val = readw(sclk->en_reg);
550 val &= BIT(sclk->en_bit);
552 return val ? 1 : 0;
557 u16 val;
559 val = readw(syscon_vbase + U300_SYSCON_CCR);
560 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
561 return val;
654 u16 val;
661 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
664 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
667 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
670 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
675 val |= readw(syscon_vbase + U300_SYSCON_CCR) &
677 writew(val, syscon_vbase + U300_SYSCON_CCR);
955 u16 val;
961 val = readw(syscon_vbase + U300_SYSCON_MMCR);
963 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
965 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
966 writew(val, syscon_vbase + U300_SYSCON_MMCR);
968 val = readw(syscon_vbase + U300_SYSCON_MMCR);
970 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
972 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
973 writew(val, syscon_vbase + U300_SYSCON_MMCR);
1011 u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
1013 switch (val) {
1067 u16 val;
1072 val = 0x0054;
1075 val = 0x0044;
1078 val = 0x0043;
1081 val = 0x0033;
1084 val = 0x0032;
1087 val = 0x0022;
1090 val = 0x0021;
1093 val = 0x0011;
1096 val = 0x0000;
1104 writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
1181 u16 val;
1186 val = readw(syscon_vbase + U300_SYSCON_CCR);
1187 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1188 writew(val, syscon_vbase + U300_SYSCON_CCR);
1194 val = readw(syscon_vbase + U300_SYSCON_PMCR);
1195 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1196 writew(val, syscon_vbase + U300_SYSCON_PMCR);