Lines Matching refs:clk_val
431 * @clk_val: magic value to poke in the register to enable/disable
442 u16 clk_val;
502 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
517 if (sclk->clk_val == 0xFFFFU)
520 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
531 if (sclk->clk_val == 0xFFFFU)
534 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
537 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
571 switch (sclk->clk_val) {
638 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
657 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
698 u16 clk_val)
722 sclk->clk_val = clk_val;
743 * @clk_val: a value to poke in the one-write enable/disable registers
749 u16 clk_val;
757 .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
763 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
769 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
775 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
781 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
787 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
793 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
800 .clk_val = 0xFFFFU,
806 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
812 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
818 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
824 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
830 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
836 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
842 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
848 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
855 .clk_val = 0xFFFFU,
861 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
867 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
920 u3clk->clk_val);