Lines Matching refs:STM32F4_RCC_CFGR
29 #define STM32F4_RCC_CFGR 0x08
420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
1182 STM32F4_RCC_CFGR, 23, 1,
1209 STM32F4_RCC_CFGR, 23, 1,
1254 STM32F4_RCC_CFGR, 23, 1,
1400 STM32F4_RCC_CFGR, 23, 1,
1784 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1787 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1791 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1797 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1848 0, base + STM32F4_RCC_CFGR, 16, 5, 0,