Lines Matching refs:STM32F4_RCC_AHB1ENR
30 #define STM32F4_RCC_AHB1ENR 0x30
56 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
57 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
58 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
59 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
60 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
61 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
62 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
63 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
64 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
65 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
66 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
67 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
68 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
69 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
70 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
71 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
72 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
73 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
74 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
75 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
76 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
77 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
78 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
135 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
136 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
137 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
138 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
139 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
140 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
141 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
142 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
143 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
144 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
145 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
146 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
147 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
148 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
149 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
150 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
151 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
152 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
153 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
154 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
155 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
156 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
157 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
216 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
217 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
218 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
219 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
220 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
221 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
222 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
223 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
224 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
225 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
226 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
227 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
228 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
229 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
230 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
231 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
232 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
233 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
234 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
235 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
236 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
237 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
238 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
290 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
291 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
292 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
293 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
294 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
295 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
296 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
297 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
298 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
299 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
300 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
301 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
302 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
303 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
304 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
305 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
306 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
307 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
308 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
309 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
310 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
311 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
312 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
1813 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +