Lines Matching defs:base
394 static void __iomem *base;
420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
637 n = (readl(base + pll->offset) >> 6) & 0x1ff;
676 val = readl(base + pll->offset) & ~(0x1ff << 6);
678 writel(val | ((n & 0x1ff) << 6), base + pll->offset);
810 pll->gate.reg = base + STM32F4_RCC_CR;
817 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
819 reg = base + pll->offset;
903 val = readl(base + STM32F4_RCC_BDCR);
904 writel(val | BIT(16), base + STM32F4_RCC_BDCR);
905 writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
1641 gate->reg = base + offset_gate;
1656 mux->reg = base + offset_mux;
1693 base = of_iomap(np, 0);
1694 if (!base) {
1731 base + STM32F4_RCC_APB2ENR, 29,
1742 base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
1745 pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
1768 base + post_div->offset,
1784 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1787 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1791 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1797 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1822 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1832 base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
1840 base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
1848 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1857 base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1899 iounmap(base);