Lines Matching refs:init
1369 struct clk_init_data init;
1469 memset(&init, 0, sizeof(init));
1470 init.name = si5351_input_names[0];
1471 init.ops = &si5351_xtal_ops;
1472 init.flags = 0;
1475 init.parent_names = &drvdata->pxtal_name;
1476 init.num_parents = 1;
1478 drvdata->xtal.init = &init;
1481 dev_err(&client->dev, "unable to register %s\n", init.name);
1487 memset(&init, 0, sizeof(init));
1488 init.name = si5351_input_names[1];
1489 init.ops = &si5351_clkin_ops;
1492 init.parent_names = &drvdata->pclkin_name;
1493 init.num_parents = 1;
1495 drvdata->clkin.init = &init;
1499 init.name);
1512 drvdata->pll[0].hw.init = &init;
1513 memset(&init, 0, sizeof(init));
1514 init.name = si5351_pll_names[0];
1515 init.ops = &si5351_pll_ops;
1516 init.flags = 0;
1517 init.parent_names = parent_names;
1518 init.num_parents = num_parents;
1521 dev_err(&client->dev, "unable to register %s\n", init.name);
1528 drvdata->pll[1].hw.init = &init;
1529 memset(&init, 0, sizeof(init));
1531 init.name = si5351_pll_names[2];
1532 init.ops = &si5351_vxco_ops;
1533 init.flags = 0;
1534 init.parent_names = NULL;
1535 init.num_parents = 0;
1537 init.name = si5351_pll_names[1];
1538 init.ops = &si5351_pll_ops;
1539 init.flags = 0;
1540 init.parent_names = parent_names;
1541 init.num_parents = num_parents;
1545 dev_err(&client->dev, "unable to register %s\n", init.name);
1571 drvdata->msynth[n].hw.init = &init;
1572 memset(&init, 0, sizeof(init));
1573 init.name = si5351_msynth_names[n];
1574 init.ops = &si5351_msynth_ops;
1575 init.flags = 0;
1577 init.flags |= CLK_SET_RATE_PARENT;
1578 init.parent_names = parent_names;
1579 init.num_parents = 2;
1584 init.name);
1599 drvdata->clkout[n].hw.init = &init;
1600 memset(&init, 0, sizeof(init));
1601 init.name = si5351_clkout_names[n];
1602 init.ops = &si5351_clkout_ops;
1603 init.flags = 0;
1605 init.flags |= CLK_SET_RATE_PARENT;
1606 init.parent_names = parent_names;
1607 init.num_parents = num_parents;
1612 init.name);