Lines Matching defs:synth

59 /* The output stages can be connected to any synth (full mux) */
73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
219 * The "known" settings like synth and output configuration are done later.
560 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
563 u8 index = synth->index;
565 err = regmap_read(synth->data->regmap,
573 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
581 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
590 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
591 u8 index = synth->index; /* In range 0..5 */
595 regmap_update_bits(synth->data->regmap,
598 regmap_update_bits(synth->data->regmap,
600 /* Disable clock input to synth (set to 1 to disable) */
601 regmap_update_bits(synth->data->regmap,
607 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
609 u8 index = synth->index;
613 err = regmap_update_bits(synth->data->regmap,
618 /* Enable clock input to synth (set bit to 0 to enable) */
619 err = regmap_update_bits(synth->data->regmap,
625 return regmap_update_bits(synth->data->regmap,
633 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
639 err = si5341_decode_44_32(synth->data->regmap,
640 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
651 f = synth->data->freq_vco;
664 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
668 f = synth->data->freq_vco;
673 f = synth->data->freq_vco;
681 static int si5341_synth_program(struct clk_si5341_synth *synth,
685 u8 index = synth->index;
687 err = si5341_encode_44_32(synth->data->regmap,
690 err = regmap_update_bits(synth->data->regmap,
695 return regmap_write(synth->data->regmap,
703 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
710 n_num = synth->data->freq_vco;
726 dev_dbg(&synth->data->i2c_client->dev,
728 synth->index, n_num, n_den,
731 return si5341_synth_program(synth, n_num, n_den, is_integer);
973 return &data->synth[idx].hw;
1193 /* Update bits for P divider and synth config */
1331 of_property_read_bool(child, "silabs,synth-master");
1691 data->synth[i].index = i;
1692 data->synth[i].data = data;
1693 data->synth[i].hw.init = &init;
1694 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1697 "synth N%u registration failed\n", i);