Lines Matching defs:input
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
44 /* The chip can get its input clock from 3 input pins or an XTAL */
50 /* The 5 frequency synthesizers obtain their input from the PLL */
217 * using only the XTAL input, without pre-divider.
224 { 0x0021, 0x0F }, /* Select XTAL as input */
354 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
475 /* Enable register-based input selection */
484 /* Enable input buffer for selected input */
490 /* Enables the input to phase detector */
506 * programs a "1" when the input is being used.
521 /* Disable all input buffers */
526 /* Disable input to phase detector */
580 /* This bit must be 0 for the synthesizer to receive clock input */
600 /* Disable clock input to synth (set to 1 to disable) */
618 /* Enable clock input to synth (set bit to 0 to enable) */
1421 /* If the current register setting is invalid, pick the first input */
1434 "No clock input available\n");
1544 struct clk *input;
1565 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1566 if (IS_ERR(input)) {
1567 if (PTR_ERR(input) == -EPROBE_DEFER)
1571 data->input_clk[i] = input;
1572 data->input_clk_name[i] = __clk_get_name(input);
1758 /* wait for device to report input clock present and PLL lock */
1763 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");