Lines Matching defs:config
120 /* XTAL config bits */
226 { 0x002B, 0x02 }, /* SPI config */
1193 /* Update bits for P divider and synth config */
1257 struct clk_si5341_output_config *config)
1264 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1283 config[num].out_cm_ampl_bits = 0x33;
1286 config[num].out_cm_ampl_bits = 0x13;
1289 config[num].out_cm_ampl_bits = 0x33;
1291 config[num].out_format_drv_bits |= 0xc0;
1299 config[num].out_format_drv_bits &= ~0x07;
1300 config[num].out_format_drv_bits |= val & 0x07;
1302 config[num].out_format_drv_bits |= 0x08;
1312 config[num].out_cm_ampl_bits &= 0xf0;
1313 config[num].out_cm_ampl_bits |= val & 0x0f;
1323 config[num].out_cm_ampl_bits &= 0x0f;
1324 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1328 config[num].out_format_drv_bits |= 0x10;
1330 config[num].synth_master =
1333 config[num].always_on =
1336 config[num].vdd_sel_bits = 0x08;
1342 config[num].vdd_sel_bits |= 0 << 4;
1345 config[num].vdd_sel_bits |= 1 << 4;
1348 config[num].vdd_sel_bits |= 2 << 4;
1361 config[num].vdd_sel_bits |= 2 << 4;
1549 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1600 err = si5341_dt_parse_dt(data, config);
1712 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1716 if (config[i].out_format_drv_bits & 0x07) {
1719 config[i].out_format_drv_bits);
1722 config[i].out_cm_ampl_bits);
1726 config[i].vdd_sel_bits);
1735 if (config[i].always_on)