Lines Matching refs:cg
72 #define CG_VER3 4 /* version 3 cg: reg layout different */
79 void (*init_periph)(struct clockgen *cg);
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
102 if (cg->info.flags & CG_LITTLE_ENDIAN)
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
112 if (cg->info.flags & CG_LITTLE_ENDIAN)
467 static void __init p2041_init_periph(struct clockgen *cg)
471 reg = ioread32be(&cg->guts->rcwsr[7]);
474 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
479 static void __init p4080_init_periph(struct clockgen *cg)
483 reg = ioread32be(&cg->guts->rcwsr[7]);
486 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
488 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
491 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
493 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
496 static void __init p5020_init_periph(struct clockgen *cg)
501 reg = ioread32be(&cg->guts->rcwsr[7]);
506 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
508 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
511 static void __init p5040_init_periph(struct clockgen *cg)
516 reg = ioread32be(&cg->guts->rcwsr[7]);
521 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
523 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
526 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
528 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
531 static void __init t1023_init_periph(struct clockgen *cg)
533 cg->fman[0] = cg->hwaccel[1];
536 static void __init t1040_init_periph(struct clockgen *cg)
538 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
541 static void __init t2080_init_periph(struct clockgen *cg)
543 cg->fman[0] = cg->hwaccel[0];
546 static void __init t4240_init_periph(struct clockgen *cg)
548 cg->fman[0] = cg->hwaccel[3];
549 cg->fman[1] = cg->hwaccel[4];
812 struct clockgen *cg;
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
868 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
880 return &cg->pll[pll].div[div];
883 static struct clk * __init create_mux_common(struct clockgen *cg,
905 div = get_pll_div(cg, hwc, i);
931 hwc->cg = cg;
944 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
956 if (cg->info.flags & CG_VER3)
957 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
959 hwc->reg = cg->regs + 0x20 * idx;
961 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
970 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
971 div = get_pll_div(cg, hwc, clksel);
981 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
983 if (cg->info.flags & CG_CMUX_GE_PLAT)
988 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
989 pct80_rate, "cg-cmux%d", idx);
992 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
1000 hwc->reg = cg->regs + 0x20 * idx + 0x10;
1001 hwc->info = cg->info.hwaccel[idx];
1003 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
1004 "cg-hwaccel%d", idx);
1007 static void __init create_muxes(struct clockgen *cg)
1011 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
1012 if (cg->info.cmux_to_group[i] < 0)
1014 if (cg->info.cmux_to_group[i] >=
1015 ARRAY_SIZE(cg->info.cmux_groups)) {
1020 cg->cmux[i] = create_one_cmux(cg, i);
1023 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
1024 if (!cg->info.hwaccel[i])
1027 cg->hwaccel[i] = create_one_hwaccel(cg, i);
1185 static void __init create_one_pll(struct clockgen *cg, int idx)
1189 struct clockgen_pll *pll = &cg->pll[idx];
1190 const char *input = "cg-sysclk";
1193 if (!(cg->info.pll_mask & (1 << idx)))
1196 if (cg->coreclk && idx != PLATFORM_PLL) {
1197 if (IS_ERR(cg->coreclk))
1200 input = "cg-coreclk";
1203 if (cg->info.flags & CG_VER3) {
1206 reg = cg->regs + 0x60080;
1209 reg = cg->regs + 0x80;
1212 reg = cg->regs + 0xa0;
1215 reg = cg->regs + 0x10080;
1218 reg = cg->regs + 0x100a0;
1226 reg = cg->regs + 0xc00;
1228 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1232 mult = cg_in(cg, reg);
1240 if ((cg->info.flags & CG_VER3) ||
1241 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1258 "cg-pll%d-div%d", idx, i + 1);
1277 static void __init create_plls(struct clockgen *cg)
1281 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1282 create_one_pll(cg, i);
1363 struct clockgen *cg = data;
1380 clk = cg->sysclk;
1383 if (idx >= ARRAY_SIZE(cg->cmux))
1385 clk = cg->cmux[idx];
1388 if (idx >= ARRAY_SIZE(cg->hwaccel))
1390 clk = cg->hwaccel[idx];
1393 if (idx >= ARRAY_SIZE(cg->fman))
1395 clk = cg->fman[idx];
1398 pll = &cg->pll[PLATFORM_PLL];
1406 clk = cg->coreclk;
1520 clockgen.sysclk = create_sysclk("cg-sysclk");
1521 clockgen.coreclk = create_coreclk("cg-coreclk");