Lines Matching defs:PLL_DIV3
24 #define PLL_DIV3 2
260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
273 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
299 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
312 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
325 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
334 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
347 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
363 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
372 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
412 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
421 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
425 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
438 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
445 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
455 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
459 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },