Lines Matching defs:PLATFORM_PLL
27 #define PLATFORM_PLL 0
257 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
270 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
283 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
296 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
336 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
410 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
423 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
431 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
447 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
457 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
488 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
493 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
508 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
523 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
528 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
538 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
981 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
1196 if (cg->coreclk && idx != PLATFORM_PLL) {
1205 case PLATFORM_PLL:
1225 if (idx == PLATFORM_PLL)
1241 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1254 if (idx != PLATFORM_PLL && i >= 4)
1337 legacy_pll_init(np, PLATFORM_PLL);
1398 pll = &cg->pll[PLATFORM_PLL];